M28C17
16K (2K x 8) PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
NOT FOR NEW DESIGN
FAST ACCESS TIME: 90ns
SINGLE 5V
±
10% SUPPLY VOLTAGE
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Ready/Busy Open Drain Output
– Data Polling
– Toggle Bit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
M28C17 is replaced by the products
described on the document M28C16A
DESCRIPTION
The M28C17 is a 2K x 8 low power Parallel
EEPROM fabricated with SGS-THOMSON pro-
prietary single polysilicon CMOS technology. The
device offers fast access time with low power dis-
sipation and requires a 5V power supply.
The M28C17 offers the same features than the
M28C16, in addition to the Ready/Busy pin.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
Table 1. Signal Names
A0 - A10
DQ0 - DQ7
W
E
G
RB
V
CC
V
SS
Address Input
Data Input / Output
Write Enable
Chip Enable
Output Enable
Ready / Busy
Supply Voltage
Ground
28
1
PDIP28 (P)
PLCC32 (K)
28
1
SO28 (MS)
300 mils
Figure 1. Logic Diagram
VCC
11
A0-A10
8
DQ0-DQ7
W
E
M28C17
RB
G
VSS
AI01487
November 1997
This is information on a product still in production but not recommended for new design.
1/17
M28C17
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
AI01506B
DQ1
DQ2
VSS
DU
DQ3
DQ4
DQ5
AI01508C
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
27
2
26
3
25
4
24
5
23
6
22
7
M28C17
21
8
20
9
19
10
18
11
17
12
13
16
14
15
VCC
W
NC
A8
A9
NC
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
RB
DU
VCC
W
NC
1 32
M28C17
25
A8
A9
NC
NC
G
A10
E
DQ7
DQ6
17
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
9
Warning:
NC = Not Connected.
Warning:
NC = Not Connected, DU = Don’t Use.
Figure 2C. SO Pin Connections
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
M28C17
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
NC
A8
A9
NC
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
DESCRIPTION
(cont’d)
and software handshaking with Ready/Busy, Data
Polling and Toggle Bit. The M28C17 supports 64
byte page write operation. A Software Data Protec-
tion (SDP) is also possible using the standard
JEDEC algorithm.
PIN DESCRIPTION
Addresses (A0-A10).
The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E).
The chip enable input must be
low to enable all read/write operations. When Chip
Enable is high, power consumption is reduced.
Output Enable (G).
The Output Enable input con-
trols the data output buffers and is used to initiate
read operations.
Data In/ Out (DQ0 - DQ7).
Data is written to or read
from the M28C17 through the I/O pins.
Write Enable (W).
The Write Enable input controls
the writing of data to the M28C17.
Ready/Busy (RB).
Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle.
AI01507B
Warning:
NC = Not Connected.
2/17
A7
NC
M28C17
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
V
CC
V
IO
V
I
V
ESD
Parameter
Ambient Operating Temperature
Storage Temperature Range
Supply Voltage
Input/Output Voltage
Input Voltage
Electrostatic Discharge Voltage (Human Body model)
(2)
Value
– 40 to 125
– 65 to 150
– 0.3 to 6.5
– 0.3 to V
CC
+0.6
– 0.3 to 6.5
4000
Unit
°C
°C
V
V
V
V
Note:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7
Table 3. Operating Modes
(1)
Mode
Standby
Output Disable
Write Disable
Read
Write
E
1
X
X
0
0
G
X
1
X
0
1
W
X
X
1
1
0
DQ0 - DQ7
Hi-Z
Hi-Z
Hi-Z
Data Out
Data In
Chip Erase
Note:
1. 0 = V
IL
; 1 = V
IH
; X = V
IL
or V
IH;
V = 12
±
5%.
0
V
0
Hi-Z
OPERATION
In order to prevent data corruption and inadvertent
write operations an internal V
CC
comparator inhibits
Write operation if V
CC
is below V
WI
(see Table 7).
Access to the memory in write mode is allowed after
a power-up as specified in Table 7.
Read
The M28C17 is accessed like a static RAM. When
E and G are low with W high, the data addressed
is presented on the I/O pins. The I/O pins are high
impedance when either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The M28C17 supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion.
Page Write
Page write allows up to 64 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A6-A10 must be the
same for all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data with a mini-
mum data transfer rate of 1/t
WHWH
(see Figure 13).
If a transition of E or W is not detected within t
WHWH
,
the internal programming cycle will start.
Chip Erase
The contents of the entire memory may be erased
to FFh by use of the Chip Erase command by
setting Chip Enable (E) Low and Output Enable
(G) to V
CC
+ 7.0V. The chip is cleared when a 10ms
low pulse is applied to the Write Enable pin.
3/17
M28C17
Figure 3. Block Diagram
RB
E
G
W
VPP GEN
RESET
CONTROL LOGIC
X DECODE
A6-A10
(Page Address)
ADDRESS
LATCH
64K ARRAY
A0-A5
ADDRESS
LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
AI01488
DQ0-DQ7
Microcontroller Control Interface
The M28C17 provides two write operation status
bits and one status pin that can be used to minimize
the system write cycle. These signals are available
on the I/O port bits DQ7 or DQ6 of the memory
during programming cycle only, or as the RB signal
on a separate pin.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Data Polling bit (DQ7).
During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Toggle bit (DQ6).
The M28C17 offers another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 will toggle from "0" to "1" and "1" to "0" (the
first read value is "0") on subsequent attempts to
read the memory. When the internal cycle is com-
pleted the toggling will stop and the device will be
accessible for a new Read or Write operation.
Page Load Timer Status bit (DQ5).
In the Page
Write mode data may be latched by E or W. Up to
64 bytes may be input. The Data output (DQ5)
indicates the status of the internal Page Load
Timer. DQ5 may be read by asserting Output En-
able Low (t
PLTS
). DQ5 Low indicates the timer is
running, High indicates time-out after which the
write cycle will start and no new data may be input.
Ready/Busy pin.
The RB pin provides a signal at
its open drain output which is low during the
erase/write cycle, but which is released at the
completion of the programming cycle.
4/17
M28C17
Figure 5. Software Data Protection Enable Algorithm and Memory Write
WRITE AAh in
Address 555h
Page
Write
Instruction
(Note 1)
Page
Write
Instruction
(Note 1)
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE 55h in
Address 2AAh
WRITE A0h in
Address 555h
WRITE A0h in
Address 555h
WRITE
is enabled
SDP is set
Write Page
(1 up to 64 bytes)
SDP ENABLE ALGORITHM
WRITE IN MEMORY
WHEN SDP IS SET
AI01509B
Note:
1. MSB Address bits (A6 to A10) differ during these specific Page Write operations.
Figure 6. Software Data Protection Disable
Algorithm
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
Page
Write
Instruction
WRITE 80h in
Address 555h
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
WRITE 20h in
Address 555h
Unprotected State
AI01510
Software Data Protection
The M28C17 offers a software controlled write
protection facility that allows the user to inhibit all
write modes to the device including the Chip Erase
instruction. This can be useful in protecting the
memory from inadvertent write cycles that may
occur due to uncontrolled bus conditions.
The M28C17 is shipped as standard in the "unpro-
tected" state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the "Protect Mode" of
operation where no further write commands have
any effect on the memory contents. The device
remains in this mode until a valid Software Data
Protection (SDP) disable sequence is received
whereby the device reverts to its "unprotected"
state. The Software Data Protection is fully non-
volatile and is not changed by power on/off se-
quences.
To enable the Software Data Protection (SDP) the
device requires the user to write (with a Page Write)
three specific data bytes to three specific memory
locations as per Figure 5. Similarly to disable the
Software Data Protection the user has to write
specific data bytes into six different locations as per
Figure 6 (with a Page Write). This complex series
ensures that the user will never enable or disable
the Software Data Protection accidentally.
5/17
京公网安备 11010802033920号
EEWORLD
