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74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable
January 2008
74AC377, 74ACT377
Octal D-Type Flip-Flop with Clock Enable
Features
■
I
CC
reduced by 50%
■
Ideal for addressable register applications
■
Clock enable for address and data synchronization
■
■
■
■
■
■
■
General Description
The AC/ACT377 has eight edge-triggered, D-type flip-
flops with individual D inputs and Q outputs. The com-
mon buffered Clock (CP) input loads all flip-flops simulta-
neously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop's Q
output. The CE input must be stable only one setup time
prior to the LOW-to-HIGH clock transition for predictable
operation.
applications
Eight edge-triggered D-type flip-flops
Buffered common clock
Outputs source/sink 24mA
See 273 for master reset version
See 373 for transparent latch version
See 374 for 3-STATE version
ACT377 has TTL-compatible inputs
Ordering Information
Order Number
74AC377SC
74AC377SJ
74AC377MTC
74ACT377SC
74ACT377SJ
74ACT377MTC
74ACT377PC
Package
Number
M20B
M20D
MTC20
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
FACT™ is a trademark of Fairchild Semiconductor Corporation
.
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
CE
Q
0
–Q
7
CP
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
Description
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs
Operating Mode
Load ‘1'
Load ‘0'
Hold (Do Nothing)
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Outputs
D
n
H
L
X
X
CP
CE
L
L
H
H
Q
n
H
L
No Change
No Change
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
2
74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
3
74AC377, 74ACT377 — Octal D-Type Flip-Flop with Clock Enable
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
AC
ACT
V
I
V
O
T
A
∆
V /
∆
t
∆
V /
∆
t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
125mV/ns
Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Rev. 1.6.1
www.fairchildsemi.com
4
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