DM5440J/883 datasheet, PDF - EEWORLD Datasheet

DM5440J/883: DescriptionIC TTL/H/L SERIES, DUAL 4-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14, Gate; Categorylogic logic; File Size99KB，3 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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DM5440J/883 Overview

IC TTL/H/L SERIES, DUAL 4-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14, Gate

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknown
Other features	IOL = 48MA @ VOL = 0.4V; IOH = 1.2MA @ VOH = 2.4V
series	TTL/H/L
JESD-30 code	R-GDIP-T14
JESD-609 code	e0
length	19.43 mm
Load capacitance (CL)	15 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.048 A
Number of functions	2
Number of entries	4
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	27 mA
Prop。Delay @ Nom-Sup	22 ns
propagation delay (tpd)	15 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	38535Q/M;38534H;883B
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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