Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MPC962308
Rev 3, 08/2004
3.3 V Zero Delay Buffer
The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom and other
high-performance applications. The MPC962308 uses an internal PLL and an
external feedback path to lock its low-skew clock output phase to the reference
clock phase, providing virtually zero propagation delay. The input-to-output
skew is guaranteed to be less than 250 ps and output-to-output skew is
guaranteed to be less than 200 ps.
Features
•
•
1:8 outputs LVCMOS zero-delay buffer
Zero input-output propagation delay, adjustable by the capacitive load on
FBK input
Multiple Configurations, see
Table 2. Available MPC962308
Configurations
Multiple low-skew outputs
200 ps max output-output skew
700 ps max device-device skew
Two banks of four outputs, output tristate control by two select inputs
Supports a clock I/O frequency range of 10 MHz to 133 MHz
Low jitter, 200 ps max cycle-cycle (-1, -1H, -4, -5H)
±250 ps static phase offset (SPO)
16-pin SOIC package or 16-pin TSSOP package
Single 3.3 V supply
Ambient temperature range: –40°C to +85°C
Compatible with the CY2308 and CY23S08
Spread spectrum compatible
MPC962308
Freescale Semiconductor, Inc...
D SUFFIX
16-LEAD SOIC PACKAGE
CASE 751B-05
•
•
•
•
•
•
•
•
•
•
•
•
•
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
Functional Description
The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in
Table 1. Select
Input Decoding.
Bank B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly
applied to the output for chip and system testing purposes. The MPC962308 PLL enters a power down state when there are no rising
edges on the REF input. During this state, all of the outputs are in tristate and there is less than 50
µA
of current draw. The PLL shuts
down in two additional cases explained in
Table 1. Select Input Decoding.
Multiple MPC962308 devices can accept and distribute the same input clock throughout the system. In this situation, the difference
between the output skews of two devices will be less than 700 ps.
The MPC962308 is available in five different configurations as shown in
Table 2. Available MPC962308 Configurations.
In the
MPC962308-1, the reference frequency is reproduced by the PLL and provided at the outputs. A high drive version of this configura-
tion, the MPC962308-1H, is available to provide faster rise and fall times of the device.
The MPC962308-2 provides 2X and 1X the reference frequency at the output banks. In addition, the MPC962308-3 provides 4X
and 2X the reference frequency at the output banks. The output banks driving the feedback will determine the different configurations
of the above devices. The MPC962308-4 provides outputs 2X the reference frequency.The MPC962308-5H is a high drive version
with outputs of REF/2.
The MPC962308 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS
signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
Ω
transmission lines on the
incident edge. Depending on the configuration, the device is offered in a 16-lead SOIC or 16-lead TSSOP package.
© Motorola, Inc. 2004
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MPC962308
Block Diagram
/2
REF
/2
Extra Divider (-3, -4)
Extra Divider (-5H)
S2
S1
Select Input
Decoding
Pin Configuration
SOIC/TSSOP
Top View
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
PLL
MUX
FBK
CLKA1
CLKA2
CLKA3
CLKA4
/2
CLKB1
CLKB2
CLKB3
Extra Divider (-2, -3)
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CLKB4
Table 1. Select Input Decoding
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1—A4
Three-State
Driven
Driven
1
Driven
CLOCK B1—B4
Three-State
Three-State
Driven
1
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
Y
N
Y
N
1. Outputs inverted on MPC962308-2 in bypass mode, S2=1 and S1=0.
Table 2. Available MPC962308 Configurations
Device
MPC962308-1
MPC962308-1H
MPC962308-2
MPC962308-2
MPC962308-3
MPC962308-3
MPC962308-4
MPC962308-5H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference /2
Bank B Frequency
Reference
Reference
Reference/2
Reference
Reference or Reference
[1]
2 X Reference
2 X Reference
Reference /2
1. Output phase is indeterminate (0° or 180° from input clock). If phase integrity is required, use the MPC962308-2.
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MPC962308
Table 3. Pin Description
Pin
1
2
3
4
5
6
7
8
REF
1
CLKA1
2
CLKA2
2
V
DD
GND
CLKB1
2
CLKB2
2
S2
3
S1
3
CLKB3
2
CLKB4
2
GND
V
DD
CLKA3
2
CLKA4
2
FBK
Signal
Description
Input reference frequency, 5 V tolerant input
Clock output, Bank A
Clock output, Bank A
3.3 V supply
Ground
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Ground
3.3 V supply
Clock output, Bank A
Clock output, Bank A
PLL feedback input
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9
10
11
12
13
14
15
16
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
Table 4. Maximum Ratings
Characteristics
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage REF
Storage Temperature
Junction
Static Discharge Voltage (per MIL-STD-883, Method 3015)
Value
–0.5 to +3.9
–0.5 to V
DD
+0.5
–0.5 to 5.5
–65 to +150
150
>2000
Unit
V
V
V
°C
°C
V
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MPC962308
Table 5. Operating Conditions for MPC962308-X Industrial Temperature Devices
Parameter
V
DD
T
A
C
L
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
C
IN
Input Capacitance
1
Description
Min
3.0
–40
Max
3.6
85
30
15
7
Unit
V
°C
pF
pF
pF
1. Applies to both REF clock and FBK.
Table 6. Electrical Characteristics for MPC962308-X Industrial Temperature Devices
1
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Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PD mode)
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
2
Output HIGH Voltage
2
Power Down Supply Current
Supply Current
V
IN
= 0V
V
IN
= V
DD
Test Conditions
Min
Max
0.8
Unit
V
V
2.0
50.0
100.0
0.4
2.4
25.0
45.0
70(-1H, -5H)
35.0
20.0
µA
µA
V
V
µA
mA
mA
mA
mA
I
OL
= 8 mA (-1, -2, -3, -4)
I
OL
= 12 mA (-1H, -5H)
I
OH
= -8 mA (-1, -2, -3, -4)
I
OH
= -12 mA (-1H, -5H)
REF = 0 MHz
Unloaded outputs, 100 MHz,
Select inputs at V
DD
or GND
Unloaded outputs, 66-MHz REF
(-1, -2, -3, -4)
Unloaded outputs, 35-MHz REF
(-1, -2, -3, -4)
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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MPC962308
Table 7. Switching Characteristics for MPC962308-X Industrial Temperature Devices
1
Parameter
t
1
t
1
t
1
Name
Output Frequency
Output Frequency
2
Output Frequency
2
Duty Cycle
2
= t
2
÷
t
1
(-1, -2, -3, -4, -1H, -5H)
Duty Cycle
2
= t
2
÷
t
1
(-1, -2, -3, -4, -1H, -5H)
t
3
Rise Time
2
(-1, -2, -3, -4)
Rise Time
2
(-1, -2, -3, -4)
Rise Time
2
(-1H, -5H)
t
4
Fall Time
2
(-1, -2, -3, -4)
Fall Time
2
(-1, -2, -3, -4)
Fall Time
2
(-1H, -5H)
Output-to-Output Skew on
same Bank (-1, -2, -3, -4)
t
5
Output-to-Output Skew
(-1H, -5H)
Output Bank A to Output
Bank B Skew (-1, -4, -5H)
Output Bank A to Output
Bank B Skew (-2, -3)
t
6
t
7
t
8
t
J
Delay, REF Rising Edge to
FBK Rising Edge
2
2
Test Conditions
30-pF load, All devices
20-pF load, -1H, -5H devices
15-pF load, -1, -2, -3, -4 devices
Measured at 1.4 V, FOUT =66.66 MHz
30-pF load
Measured at 1.4 V, FOUT <50.0 MHz
15-pF load
Measured between 0.8 V and 2.0 V,
30-pF load
Measured between 0.8 V and 2.0 V,
15-pF load
Measured between 0.8 V and 2.0 V,
30-pF load
Measured between 0.8 V and 2.0 V,
30-pF load
Measured between 0.8 V and 2.0 V,
15-pF load
Measured between 0.8 V and 2.0 V,
30-pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of devices
Measured between 0.8 V and 2.0 V on -1H,
-5H device using Test Circuit # 2
Measured at 66.67 MHz, loaded outputs,
15-pF load
Measured at 66.67 MHz, loaded outputs,
30-pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
Min
10
10
10
40.0
45.0
Typ
Max
100
133.3
133.3
60.0
55.0
2.50
1.50
1.50
2.50
1.50
1.25
200
200
200
400
Unit
MHz
MHz
MHz
%
%
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
V/ns
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0
0
1
±250
700
Device-to-Device Skew
2
Output Slew Rate
2
Cycle-to-Cycle Jitter
(-1, -1H, -4, -5H)
2
200
200
100
400
400
1.0
ps
ps
ps
ps
ps
ms
t
J
Cycle-to-Cycle Jitter
(-2, -3)
2
Measured at 66.67 MHz, loaded outputs
30-pF load
Measured at 66.67 MHz, loaded outputs
15-pF load
t
LOCK
PLL Lock Time
2
Stable power supply, valid clocks presented
on REF and FBK pins
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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