CMOS Static RAM
256K (32K x 8-Bit)
Features
71256S
71256L
◆
◆
◆
◆
◆
◆
◆
◆
◆
High-speed address/chip select time
– Commercial: 20/25/35ns (max.)
– Industrial: 20/25/35ns (max.)
– Military: 25/35/45/55/70/85/100ns (max.)
Low-power operation
Battery Backup operation – 2V data retention
Produced with advanced high-performance CMOS
technology
Input and output directly TTL-compatible
Available in standard 28-pin (300 or 600 mil) ceramic DIP,
28-pin (300 mil) SOJ
Military product compliant to MIL-STD-883, Class B
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
The IDT 71256 is a 262,144-bit high-speed static RAM organized as
32K x 8. It is fabricated using high-performance, high-reliability CMOS
technology.
Address access times as fast as 20ns are available with power
consumption of only 350mW (typ.). The circuit also offers a reduced power
standby mode. When
CS
goes HIGH, the circuit will automatically go to and
remain in, a low-power standby mode as long as
CS
remains HIGH. This
capability provides significant system level power and cooling savings.
The low-power (L) version also offers a battery backup data retention
capability where the circuit typically consumes only 5μW when operating
off a 2V battery.
The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP,
a 28-pin 300 mil SOJ providing high board level packing densities.
The IDT71256 military RAM is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
Description
Functional Block Diagram
A
0
ADDRESS
DECODER
A
14
262,144 BIT
MEMORY ARRAY
V
CC
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
CS
OE
WE
,
CONTROL
CIRCUIT
2946 drw 01
1
Aug.06.20
71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Pin Configurations
(1)
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
Truth Table
(1)
WE
CS
H
V
HC
L
L
L
OE
X
X
H
L
X
I/O
High-Z
High-Z
High-Z
D
OUT
D
IN
Function
Standby (I
SB
)
Standby (I
SB1
)
Output Disabled
Read Data
Write Data
2946 tbl 02
71256S/L
SD28
CD28
PJG28
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
2946 drw 02
X
X
H
H
L
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power
Dissipation
DC Output Current
Com'l.
Ind.
Mil.
Unit
V
-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0
DIP/SOJ
Top View
NOTE:
1. This text does not indicate orientation of actual part-marking.
T
A
T
BIAS
T
STG
P
T
I
OUT
0 to +70
-40 to +85
-55 to +125
o
C
C
C
Pin Descriptions
Name
A
0
- A
14
I/O
0
- I/O
7
CS
WE
OE
GND
V
CC
Description
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
Ground
Power
2946 tbl 01
-55 to +125 -55 to +125 -65 to +135
-55 to +125 -55 to +125 -65 to +150
1.0
50
1.0
50
1.0
50
o
o
W
mA
2946 tbl 03
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
11
11
Unit
pF
pF
2946 tbl 04
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
2
Aug.06.20
71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Military
Industrial
Commercial
Temperature
-55
O
C to +125
O
C
-40
O
C to +85
O
C
0
O
C to +70
O
C
GND
0V
0V
0V
Vcc
5V ± 10%
5V ± 10%
5V ± 10%
2946 tbl 05
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
0.8
Unit
V
V
V
V
2946 tbl 06
NOTE:
1. V
IL
(min.) = –3.0V for pulse width less than 20ns, once per cycle.
DC Electrical Characteristics
(1,2)
(V
CC
= 5.0V ± 10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
71256S/L20
Power
Symbol
I
CC
Parameter
Dynamic Op e rating Curre nt
CS
< V
IL
, Outp uts Op e n
V
CC
= Max., f
MAX
(2)
Stand b y Po we r Sup p ly Curre nt
(TTL Le ve l),
CS
> V
IH
, V
CC
= Max.,
Outp uts Op e n, f = f
MAX
(2)
Full Stand b y Po we r Sup p ly Curre nt
(CMOS Le ve l),
CS
> V
HC
,
V
CC
= Max., f = 0
S
L
S
L
S
L
Com'l.
& Ind
____
71256S/L25
Com'l
& Ind
____
71256S/L35
Com'l.
& I nd
____
71256S/L45
Mi l .
Unit
135
115
20
3
20
1.5
2946 tb l 07
Mi l .
150
130
20
3
20
1.5
Mi l .
140
120
20
3
20
1.5
mA
135
____
125
____
115
____
I
SB
mA
3
____
3
____
3
____
I
SB1
mA
0.6
0.6
0.6
71256S/L55
Symbol
I
CC
Parameter
Dynamic Operating Current
CS
< V
IL
, Outputs Open
V
CC
= Max., f
MAX
(2)
Standby Power Supply Current
(TTL Level),
CS
> V
IH
, V
CC
= Max.,
Outputs Open, f = f
MAX
(2)
Full Standby Power Supply Current
(CMOS Level),
CS
> V
HC
,
V
CC
= Max., f = 0
Power
S
L
S
L
S
L
Mil.
135
115
20
3
20
1.5
71256S/L70
Mil.
135
115
20
3
20
1.5
71256S/L85
Mil.
135
115
20
3
20
1.5
71256S/L100
Mil.
135
115
20
3
20
1.5
2946 tbl 08
Unit
mA
I
SB
mA
I
SB1
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
, all address inputs are cycling at f
MAX
; f = 0 means no address pins are cycling.
6.42
3
Aug.06.20
71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2946 tbl 09
5V
480Ω
DATA
OUT
255Ω
30pF*
DATA
OUT
255Ω
5V
480Ω
5pF*
,
2946 drw 04
2946 drw 05
,
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ,
t
OHZ
, t
OW
, and t
WHZ
)
Figure 1. AC Test Load
*Includes scope and jig capacitances
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
IDT71256S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
V
CC
= Max.,
V
IN =
GND to V
CC
V
CC
= Max.,
CS
= V
IH
,
V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OL
= 10mA, V
CC
= Min.
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
MIL.
COM"L & IND.
MIL.
COM"L & IND.
Min.
____
____
____
____
____
____
IDT71256L
Max.
10
5
10
5
0.4
0.5
____
Typ.
____
____
____
____
____
____
____
Min.
____
____
____
____
____
____
Typ.
____
____
____
____
____
____
____
Max.
5
2
5
2
0.4
0.5
____
Unit
µA
µA
V
2.4
2.4
V
2946 tbl 10
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
Typ.
(1)
V
CC
@
Symbol
V
DR
I
CCDR
t
CDR
t
R
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CS
> V
HC
Test Condition
____
Max.
V
CC
@
3.0V
____
____
____
____
Min.
2.0
____
____
2.0V
____
____
____
____
2.0V
____
3.0V
____
Unit
V
μA
ns
ns
2946 tbl 11
MIL.
COM'L. & IND.
500
120
____
800
200
____
0
t
RC
(2)
____
____
____
____
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
4
Aug.06.20
71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Low V
CC
Data Retention Waveform
DATA
RETENTION
MODE
V
CC
t
CDR
CS
V
IH
4.5V
V
DR
≥
2V
V
IH
2946 drw 06
4.5V
t
R
V
DR
AC Electrical Characteristics
(V
CC
= 5.0V ± 10%, All Temperature Ranges)
71256L20
(1)
Symbol
Parameter
Min.
Max.
71256S25
71256L25
Min.
Max.
71256S35
71256L35
Min.
Max.
71256S45
(3)
71256L45
(3)
Min.
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
(2)
t
CHZ
(2)
t
OE
t
OLZ
(2)
t
OHZ
(2)
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Desele ct to Output in High-Z
Output Enable to Output Valid
Output Enab le to Output in Low-Z
Output Disab le to Output in High-Z
Output Hold from Address Change
20
____
____
____
25
____
____
____
35
____
____
____
45
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
____
25
25
____
35
35
____
45
45
____
5
____
____
5
____
____
5
____
____
5
____
____
10
10
____
11
11
____
15
15
____
20
20
____
2
2
5
2
2
5
2
2
5
0
____
8
____
10
____
15
____
20
____
5
Write Cycle
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
WHZ
(2)
t
DH
t
OW
(2)
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Write Enab le to Output in High-Z
Data Hold from Write Time
Output Active from End-of-Write
20
15
15
0
15
0
11
____
____
____
____
____
____
____
____
25
20
20
0
20
0
13
____
____
____
____
____
____
____
____
35
30
30
0
30
0
15
____
____
____
____
____
____
____
____
45
40
40
0
35
0
20
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2946 tbl 12
10
____
____
11
____
____
15
____
____
20
____
____
0
5
0
5
0
5
0
5
NOTES:
1. 0° to +70°C or -40° to +85°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. –55°C to +125°C temperature range only.
6.42
5
Aug.06.20
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