54ACT818 8-Bit Diagnostic Register
September 1998
54ACT818
8-Bit Diagnostic Register
General Description
The ’ACT818 is a high-speed, general-purpose pipeline reg-
ister with an on-board diagnostic register for performing se-
rial diagnostics and/or writable control store loading.
The D-to-Y path provides an 8-bit parallel data path pipeline
register for normal system operation. The diagnostic register
can load parallel data to or from the pipeline register and can
output data through the D input port (as in WCS loading).
The 8-bit diagnostic register has multiplexer inputs that se-
lect parallel inputs from the Y-port or adjacent bits in the di-
agnostic register to operate as a right-shift-only register. This
register can then participate in a serial loop throughout the
system where normal data, address, status and control reg-
isters are replaced with ’ACT818 diagnostic pipeline regis-
ters. The loop can be used to scan in a complete test routine
starting point (Data, Address, etc.). Then after a specified
number of machine cycles it scans out the results to be in-
spected for the expected results. WCS loading can be ac-
complished using the same technique. An instruction word
can be serially shifted into the shadow register and written
into the WCS RAM by enabling the D output.
n
Swaps the contents of diagnostic register and output
register
n
Diagnostic register and diagnostic testing
n
Cascadable for wide control words as used in
microprogramming
n
Edge-triggered D registers
n
Outputs source/sink 24 mA
n
’ACT818 has TTL-compatible inputs
n
’ACT818 is functionally- and pin-compatible to AMD
Am29818 and MMI 74S818
n
Standard Microcircuit Drawing (SMD) 5962-9160901
Applications
n
n
n
n
n
n
n
n
Register for microprogram control store
Status register
Data register
Instruction register
Interrupt mask register
Pipeline register
General purpose register
Parallel-serial/serial-parallel converter
Features
n
On-line and off-line system diagnostics
Logic Symbol
DS100251-3
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
™
is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100251
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Block Diagram
DS100251-5
Functional Description
Data transfers into the diagnostic register occur on the
LOW-to-HIGH transition of DCLK. Mode and SDI determine
what data source will be loaded. The pipeline register is
loaded on the LOW-to-HIGH transition of PCLK. Mode se-
lects whether the data source is the data input or the diag-
nostic register output. Because of the independence of the
clock inputs, data can be shifted in the diagnostic register via
DCLK and loaded into the pipeline register from the data in-
put via PCLK simultaneously, as long as no setup or hold
times are violated. This simultaneous operation is legal.
Function Table
Inputs
SDI
X
X
L
X
H
MODE
L
L
H
H
H
DCLK
N
X
N
X
N
PCLK
X
N
X
N
X
SDO
S7
S7
L
SDI
H
Outputs
Diagnostic Reg.
SI
<
SI − 1,
SO
<
SD
I
NA
SI
<
YI
NA
Hold
Pipeline Reg.
NA
PI
<
DI
NA
PI
<
SI
NA
Serial Shift; D
7
–D
0
Disabled
Normal Load Pipeline Register
Load Diagnostic Register from Y;
DI Disabled
Load Pipeline Register from
Diagnostic Register
Hold Diagnostic Register; DI
Enabled
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Clock Transition
Operation
3
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
CDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to V
CC
+0.5V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
54ACT
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−55˚C to +125˚C
125 mV/ns
±
50 mA
±
50 mA
−65˚C to +150˚C
175˚C
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
™
circuits outside databook specifications.
Note 2:
All outputs loaded; thresholds on input associated with output under
test.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
V
CC
(V)
V
IH
V
IL
I
IN
I
OZ
I
CC
I
CCT
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Maximum Input
Leakage Current
Maximum TRI-STATE
Leakage Current
Maximum Quiescent
Supply Current
Maximum Additional
I
CC
/Input
Minimum HIGH
Level Output Voltage,
Y
0
–Y
7
Outputs
Minimum HIGH
Level Output Voltage,
D
0
–D
7
, SDO Outputs
V
OL
Maximum LOW
Level Output Voltage,
Y
0
–Y
7
Outputs
Maximum LOW
Level Output Voltage,
D
0
–D
7
, SDO Outputs
4.5
5.5
0.50
0.50
V
V
I
OL
= 8 mA
I
OL
= 8 mA
4.5
5.5
0.50
0.50
V
V
4.5
5.5
3.70
4.70
V
V
I
OH
= −8 mA
I
OH
= −8 mA
(Note 2)
V
IN
= V
IL
or V
IH
I
OL
= 24 mA
I
OL
= 24 mA
4.5
5.5
3.70
4.70
V
V
5.5
1.6
mA
V
IN
= V
CC
− 2.1V
V
CC
= 5.5V
(Note 2)
V
IN
= V
IL
or V
IH
I
OH
= −24 mA
I
OH
= −24 mA
5.5
160
µA
5.5
4.5
5.5
4.5
5.5
5.5
54ACT
T
A
=
−55˚C to +125˚C
Guaranteed Limits
2.0
2.0
0.8
0.8
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
OUT
= 0.1V
µA
µA
or V
CC
− 0.1V
V
IN
= V
CC
OE = V
IH
V
OUT
= 0V, V
CC
V
IN
= V
CC
or GND
Units
Conditions
±
1.0
±
1.0
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