K6F8016V3A Family
Document Title
CMOS SRAM
512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0
Initial draft
-Design Target
Finalize
Draft Date
July 4, 2001
Remark
Preliminary
1.0
September 26, 2001
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
September 2001
K6F8016V3A Family
FEATURES
•
Process Technology: Full CMOS
•
Organization: 512K x16
•
Power Supply Voltage: 3.0~3.6V
•
Low Data Retention Voltage: 1.5V(Min)
•
Three State Outputs
•
Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6F8016V3A families are fabricated by SAMSUNG′s
advanced full CMOS process technology. The families support
various operating temperature ranges. The families also sup-
port low data retention voltage for battery back-up operation
with low data retention current.
512K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM
PRODUCT FAMILY
Power Dissipation
Product Family
K6F8016V3A-F
Operating Temperature
Industrial(-40~85°C)
Vcc Range
3.0~3.6V
Speed
Standby
(I
SB1
, Typ.)
0.5µA
2)
Operating
(I
CC1
, Max)
4mA
PKG Type
44-TSOP2-400F/R
55
1)
/70ns
1. The parameter is measured with 30pF test load.
2. Typical values are measured at V
CC
=3.3V, T
A
=25°C and not 100% tested.
PIN DESCRIPTION
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
A12
A13
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
A12
A13
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CS
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A18
A17
A16
A15
A14
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
Vcc
Vss
Row
Addresses
44-TSOP2
Forward
44-TSOP2
Reverse
Row
select
Memory array
1024 rows
512×16 columns
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
I/O Circuit
Column select
I/O
9
~I/O
16
Name
CS
OE
WE
A
0
~A
18
Function
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Name
Vcc
Vss
UB
LB
Function
Power
Ground
Upper Byte(I/O
9
~
16
)
Lower Byte(I/O
1
~
8
)
CS1
CS2
OE
WE
UB
LB
Column Addresses
Control Logic
I/O
1
~I/O
16
Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 1.0
September 2001
K6F8016V3A Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
K6F8016V3A-TF55
K6F8016V3A-TF70
K6F8016V3A-RF55
K6F8016V3A-RF70
Function
CMOS SRAM
44-TSOP2-F, 55ns, 3.3V
44-TSOP2-F, 70ns, 3.3V
44-TSOP2-R, 55ns, 3.3V
44-TSOP2-R, 70ns, 3.3V
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
L
L
L
L
L
OE
X
H
X
L
L
L
X
X
X
WE
X
H
X
H
H
H
L
L
L
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
I/O
1~8
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O
9~16
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Note : X means don
′
t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.2 to V
CC
+0.3V(max.4.0V)
-0.2 to 4.0
1.0
-65 to 150
-40 to 85
Unit
V
V
W
°C
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
September 2001
K6F8016V3A Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
3.0
0
2.2
-0.3
3)
Typ
3.3
0
-
-
CMOS SRAM
Max
3.6
0
Vcc+0.3
2)
0.6
Unit
V
V
V
V
Note:
1. Industrial products: T
A
=-40 to 85°C, otherwise specified.
2. Overshoot: V
CC
+2.0V in case of pulse width
≤20ns.
3. Undershoot: -2.0V in case of pulse width
≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(CMOS)
V
OL
V
OH
I
SB1
V
IN
=Vss to Vcc
CS=V
IH,
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL,
WE=V
IH
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100%duty, I
IO
=0mA, CS≤0.2V,
V
IN
≤0.2V
or V
IN
≥VCC-0.2V
Cycle time=Min, I
IO
=0mA, 100% duty,
CS=V
IL
, VIN=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
CS≥Vcc-0.2V, Other inputs=0~Vcc
Test Conditions
Min
-1
-1
-
-
-
-
2.4
-
Typ
1)
-
-
-
-
-
-
-
0.5
Max
1
1
2
4
45
0.4
-
30
Unit
µA
µA
mA
mA
mA
V
V
µA
1. Typical values are measured at V
CC
=3.3V, T
A
=25°C and not 100% tested.
4
Revision 1.0
September 2001
K6F8016V3A Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM
3)
R
1
2)
C
L
1)
R
2
2)
1. Including scope and jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.8V
AC CHARACTERISTICS
(Vcc=3.0~3.6V)
Speed Bins
Parameter List
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
Read
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
UB, LB Valid to End of Write
Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
BLZ
t
OLZ
t
HZ
t
BHZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
BW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
-
10
5
5
0
0
0
10
55
45
0
45
45
40
0
0
25
0
5
55ns
Max
-
55
55
25
25
-
-
-
20
20
20
-
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
-
10
5
5
0
0
0
10
70
60
0
60
60
50
0
0
30
0
5
70ns
Max
-
70
70
35
35
-
-
-
25
25
25
-
-
-
-
-
-
-
-
20
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS
1
≥Vcc-0.2V
1)
Vcc=1.5V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Min
1.5
-
0
tRC
Typ
2)
-
0.5
-
-
Max
3.6
6
-
-
Unit
V
µA
ns
1. CS
1
≥Vcc-0.2V,CS
2
≥
Vcc-0.2V(CS
1
controlled) or CS
2
≥
Vcc-0.2V(CS
2
controlled).
2. Typical value are measured at T
A
=25°C and not 100% tested.
5
Revision 1.0
September 2001
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