Micrel, Inc.
D FLIP-FLOP
SuperLite™
SY55852U
SuperLite™
SY55852U
FEATURES
s
2.5GHz min. f
MAX
s
2.3V to 5.7V power supply
s
Single bit register memory
s
Synchronizes 1 bit of data to a clock
s
Optimized to work with SuperLite™ family
s
Fully differential
s
Accepts CML, PECL, LVPECL input logic levels
s
Source terminated CML outputs for fast edge rates
s
Available in a tiny 10-pin MSOP
SuperLite™
DESCRIPTION
The SY55852U is a flip-flop used to synchronize data
to a clock. Its differential output will reproduce and
remember the value on its input at the rising edge of the
clock. In addition, an asynchronous, level sensitive reset
is provided. For a synchonous reset, the SY55851U
AnyGate™ can be used.
SY55852U inputs can be terminated with a single
resistor between the true and complement pins of a given
input.
The SY55852U is a member of Micrel's SuperLite™
family of high-speed CML logic. This family features very
small packaging and 2.3V to 5.7V operation.
APPLICATIONS
s
High-speed logic
s
OC-48 communication systems
FUNCTIONAL BLOCK DIAGRAM
DATA
CLOCK
D
Q
OUT
R
RESET
SuperLite is a trademark of Micrel, Inc.
M9999-110705
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: November 2005
Micrel, Inc.
SuperLite™
SY55852U
PACKAGE/ORDERING INFORMATION
VCC /R
9
10
R
8
Q
7
/Q
6
Ordering Information
(1)
Part Number
Package
Type
K10-1
K10-1
K10-1
K10-1
K10-1
K10-1
Operating
Range
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
Package
Marking
55852U
55852U
55852U
55852U
Lead
Finish
Sn-Pb
Sn-Pb
Sn-Pb
Sn-Pb
Top View
MSOP
SY55852UKC
SY55852UKCTR
(2)
SY55852UKI
SY55852UKITR
(2)
SY55852UKG
(3)
1
D
4
5
2
3
/D CLK /CLK GND
10-Pin MSOP (K10-1)
SY55852UKGTR
(2, 3)
55852U with
NiPdAu
Pb-Free bar line indicator Pb-Free
55852U with
NiPdAu
Pb-Free bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
PIN DESCRIPTION
Pin Number
1, 2
3, 4
5
6, 7
8, 9
10
Pin Name
D, /D
CLK, /CLK
GND
Q, /Q
R, /R
VCC
Pin Function
CML/PECL/LVPECL Input (Differential): This is the single bit of data that gets clocked
in and remembered.
CML/PECL/LVPECL Input (Differential): The rising edge of this signal is the clock
signal that determines when the Boolean value at the data input gets stored.
Ground.
CML Output (Differential): This is the output of the flip-flop.
CML/PECL/LVPECL Input (Differential): This is an asynchronous active high level
reset, that forces the flip-flop into a known state, namely zero.
Power Supply.
TRUTH TABLE
D
X
X
X
0
1
CLK
X
0
1
R
1
0
0
0
0
Q
0
Q
N-1
Q
N-1
0
1
/Q
1
/Q
N-1
/Q
N-1
1
0
M9999-110705
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
SuperLite™
SY55852U
FUNCTIONAL DESCRIPTION
Establishing Static Logic Inputs
The true pin of an input pair is internally biased to ground
through a 75kΩ resistor. The complement pin of an input
pair is internally biased halfway between V
CC
and ground
by a voltage divider consisting of two 75kΩ resistors. To
keep an input at static logic zero at V
CC
> 3.0V, leave both
inputs unconnected. For V
CC
≤
3.0V, connect the
complement inputs to V
CC
and leave the true inputs
unconnected. To make an input static logic one, connect
the true input to V
CC
, leave the complement input
unconnected. These are the only safe ways to cause inputs
to be at a static value. In particular, no input pin should be
directly connected to ground. All NC (no connect) pins
should be unconnected.
V
CC
NC
X
/X
NC
NC
X
/X
Figure 1. Hard Wiring a Logic “1”
(1)
Note 1.
X is either D, CLK, R input. /X is either /D, /CLK, /R input.
V
CC
> 3.0V
NC
V
CC
X
/X
V
CC
≤
3.0V
Figure 2. Hard Wiring a Logic “0”
(1)
M9999-110705
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
SuperLite™
SY55852U
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
) .................................. –0.5V to +6.0V
CML Output Voltage .......................... V
CC
–1.0 to V
CC
+0.5
Lead Temperature (soldering, 20 sec.) ..................... 260°C
Storage Temperature (T
S
) ....................... –65°C to +150°C
Operating Ratings
(Note 2)
Supply Voltage (V
IN
) .............................. –0.5 to V
CC
+0.5V
Ambient Temperature (T
A
) ......................... –40°C to +85°C
Package Thermal Resistance
MSOP (θ
JA
)
Still-Air ........................................................... 113°C/W
500lpfm ............................................................ 96°C/W
Note 1.
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng
conditions for extended periods may affect device reliability.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 2.
DC ELECTRICAL CHARACTERISTICS
(Note 1)
V
CC
= +2.3V to +5.7V; GND = 0V; T
A
= –40°C to +85°C; unless otherwise noted.
Symbol
V
CC
I
CC
Note 1.
Parameter
Power Supply Voltage
Power Supply Current
Condition
Min
2.3
Typ
Max
5.7
36
Units
V
mA
The device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device
is tested in a socket such that transverse airflow of
≥500lfpm
is maintained.
CML DC ELECTRICAL CHARACTERISTICS
(Note 1)
V
CC
= +2.3V to +5.7V; GND = 0V; T
A
= –40°C to +85°C; unless otherwise noted.
Symbol
V
ID
V
IH
V
IL
V
OH
V
OL
V
OS
Parameter
Differential Input Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing
Note 2
Note 2
No Load
No Load
No Load,
Note 3
50Ω Environment,
Note 4
100Ω Environment,
Note 5
Condition
Min
100
1.6
1.5
—
—
V
CC
V
CC
– 0.1
V
CC
0.950
Typ
Max
Units
mV
V
V
V
V
V
V
V
Ω
V
CC
– 0.020 V
CC
– 0.010
0.660
0.800
0.400
0.200
100
V
CC
– 0.97 V
CC
– 0.825 V
CC
– 0.660
R
DRIVE
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Output Source Impedance
Equilibrium temperature.
Inputs must be biased to logic LOW or HIGH when V
CC
is less than 3.0V.
80
120
Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a 400mV swing is available in the 100Ω
environment and a 200mV swing in the 50Ω environment. Refer to the
“CML Termination”
diagram for more details.
See Figure 3a and 3b.
See Figure 4.
M9999-110705
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
SuperLite™
SY55852U
AC ELECTRICAL CHARACTERISTICS
(Note 1)
V
CC
= 2.3V to 5.7V; GND = 0V; T
A
= –40°C to +85°C; unless noted.
Symbol
f
MAX
t
pd
t
S
t
H
t
RR
t
PW
Parameter
Max. Operating Frequency
Propagation Delay
Set-Up Time
Hold Time
Reset Recovery
Minimum Pulse Width
CLK to Q
R to Q
t
r
,t
f
Note 1.
Condition
Min
2.5
Typ
Max
Units
GHz
CLK to Q
R to Q
40
40
400
V
CC
< 3V
V
CC
≥
3V
160
140
250
35
400
500
ps
ps
ps
ps
ps
CML Output Rise/Fall Times
(20% to 80%)
Tested using environment of Figure 3b, 50Ω load CML output.
150
ps
TIMING DIAGRAMS
CLK
tH
50%
DATA
tS
50%
RESET
tRR
Q
50%
tpd
50%
tpd
M9999-110705
hbwhelp@micrel.com or (408) 955-1690
5
PCB Design
京公网安备 11010802033920号
EEWORLD
