HSP50210JC-52 datasheet, PDF - EEWORLD Datasheet

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HSP50210JC-52: DescriptionSPECIALTY TELECOM CIRCUIT, PQCC84; Categorysemiconductor Analog mixed-signal IC; File Size340KB，49 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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SPECIALTY TELECOM CIRCUIT, PQCC84

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HSP50210

Data Sheet

January 1999

File Number

3652.4

Digital Costas Loop

The Digital Costas Loop (DCL) performs many of the

baseband processing tasks required for the demodulation of

BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM

waveforms. These tasks include matched ﬁltering, carrier

tracking, symbol synchronization, AGC, and soft decision

slicing. The DCL is designed for use with the HSP50110

Digital Quadrature Tuner to provide a two chip solution for

digital down conversion and demodulation.

The DCL processes the In-phase (I) and quadrature (Q)

components of a baseband signal which have been digitized

to 10 bits. As shown in the block diagram, the main signal

path consists of a complex multiplier, selectable matched

ﬁlters, gain multipliers, cartesian-to-polar converter, and soft

decision slicer. The complex multiplier mixes the I and Q

inputs with the output of a quadrature NCO. Following the

mix function, selectable matched ﬁlters are provided which

perform integrate and dump or root raised cosine ﬁltering

(α ~ 0.40). The matched ﬁlter output is routed to the slicer,

which generates 3-bit soft decisions, and to the cartesian-to-

polar converter, which generates the magnitude and phase

terms required by the AGC and Carrier Tracking Loops.

The PLL system solution is completed by the HSP50210

error detectors and second order Loop Filters that provide

carrier tracking and symbol synchronization signals. In

applications where the DCL is used with the HSP50110,

these control loops are closed through a serial interface

between the two parts. To maintain the demodulator

performance with varying signal power and SNR, an internal

AGC loop is provided to establish an optimal signal level at

the input to the slicer and to the cartesian-to-polar converter.

Features

• Clock Rates Up to 52MHz

• Selectable Matched Filtering with Root Raised Cosine or

Integrate and Dump Filter

• Second Order Carrier and Symbol Tracking Loop

Filters

• Automatic Gain Control (AGC)

• Discriminator for FM/FSK Detection and Discriminator

Aided Acquisition

• Swept Acquisition with Programmable Limits

• Lock Detector

• Data Quality and Signal Level Measurements

• Cartesian to Polar Converter

• 8-Bit Microprocessor Control - Status Interface

• Designed to work with the HSP50110 Digital

Quadrature Tuner

• 84 Lead PLCC

Applications

• Satellite Receivers and Modems

• BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM

Demodulators

• Digital Carrier Tracking

• Related Products: HSP50110 Digital Quadrature Tuner,

D/A Converters HI5721, HI5731, HI5741

• HSP50110/210EVAL Digital Demod Evaluation Board

Block Diagram

CARRIER

TRACK

CONTROL

HI/LO

(COF)

CARRIER ACQ/TRK

LOOP FILTER

NCO

COS SIN

I SER OR

(9-0)

SERCLK

OR CLK

Q SER OR

(9-0)

SYMBOL

TRACK

CONTROL

CONTROL/

STATUS

BUS

(SOF)

RRC

FILTER

INTEGRATE/

DUMP

INTEGRATE/

DUMP

CARTESIAN

POLAR

8 MAGNITUDE

PHASE

SLICER

LOOP

FILTER

CARRIER PHASE

ERROR DETECT

LEVEL

DETECT

DATA PATH MULTIPLEXER

LOCK

DETECT

LKINT

THRESH

OUT(9-0)

LEVEL

DETECT

RRC

FILTER

OUT(9-0)

SMBLCLK

OEA

OEB

SYMBOL

TRACKING

LOOP FILTER

CONTROL

INTERFACE

SYMBOL

PHASE

ERROR

DETECT

3-253

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

HSP50210

Pin Description

NAME

GND

IIN9-0

QIN9-0

SYNC

COF

TYPE

+5V Power Supply.

Ground.

In-Phase Parallel Input. Data may be two’s complement or offset binary format (see Table 14). These inputs are

sampled by CLK when the SYNC signal is active Low. IIN9 is the MSB. See Input Controller Section.

Quadrature Parallel Input. Data may be two’s complement or offset binary format (see Table 14). These inputs are

sampled by CLK when the SYNC signal is active Low. QIN9 is the MSB. See Input Controller Section.

Data Sync. When SYNC is asserted “Low”, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the

rising edge of CLK.

Carrier Offset Frequency. The frequency term generated by the Carrier Tracking Loop Filter is output serially via this

pin. The new offset frequency is shifted out MSB ﬁrst by CLK or SLOCLK starting with the clock cycle after the

assertion of COFSYNC.

Carrier Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data

word. (Programmable Polarity, see Table 41, bit 11).

Sampler Offset Frequency. Sample frequency correction term generated by the Symbol Tracking Loop Filter is output

serially via this pin. The frequency word is shifted out MSB ﬁrst by CLK or SLOCLK starting with the clock cycle after

assertion of SOFSYNC.

Sampler Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial

data word. (Programmable Polarity, see Table 41, bit 12).

Address Bus. The address on these pins specify a target register for reading or writing (see Microprocessor Interface

Section). A0 is the LSB.

Microprocessor Interface Data Bus. This bi-directional bus is used for reading and writing to the processor interface.

These are the data I/O pins for the processor interface. C0 is the LSB.

Write. This is the write strobe for the processor interface (see Microprocessor Interface Section).

Read. This is the read enable for the processor interface (see Microprocessor Interface Section).

Freeze Symbol Tracking Loop. Asserting this pin “high” zeroes the sampling error into the Symbol Tracking Loop

Filter (see Symbol Tracking Loop Filter Section).

Freeze Carrier Tracking Loop. Asserting this pin “high” zeroes the carrier Phase Error input to the Carrier Tracking

Loop Filter.

Lock Detect Interrupt. This pin is asserted “high” for at least 4 CLK cycles when the Lock Detector Integration cycle

is ﬁnished (see Lock Detector Section). Used as an interrupt for a processor. The Lock Detect Interrupt may be

asserted “high” longer than 4 CLK cycles, depending on the Lock Detector mode.

Threshold Exceeded. This output is asserted “low” when the magnitude out of the Cartesian to Polar converter

exceeds the programmable Power Detect Threshold (see Table 15 and AGC Section).

Slow Clock. Optional serial clock used for outputting data from the Carrier and Symbol Tracking Loop Filters. The

clock is programmable and has a 50% duty cycle.

Note: Not used when the HSP50110 is used with the

HSP50210 (see Table 41).

In-Phase Serial Input. Serial data input for In-Phase Data. Data on this pin is shifted in MSB ﬁrst and is synchronous

to SERCLK (see Input Controller Section).

Quadrature Serial Input. Serial data input for Quadrature Data. Data on this pin is shifted in MSB ﬁrst and is

synchronous to SERCLK (see Input Controller Section).

Serial Word Sync. This input is asserted “high” one CLK before the ﬁrst data bit of the serial word (see Figure 2).

Serial Clock. May be asynchronous to other clocks. Used to clock in serial data (see Input Controller Section).

A Output. Data on this output depend on the configuration of Output Selector. AOUT9 is the MSB (see Table 42).

B Output. Data on this output depend on the configuration of Output Selector. BOUT9 is the MSB (see Table 42).

Symbol Clock. 50% duty cycle clock aligned with soft bit decisions (see Figure 19).

A Output Enable. This pin is the three-state control pin for the AOUT9-0. When OEA is high, the AOUT9-0 is high

impedance.

B Output Enable. This pin is the three-state control pin for the BOUT9-0. When OEB is high, the AOUT9-0 is high

impedance.

HI/LO. The output of the Input Level Detector is provided on this pin (see Input Level Detector Section). This signal

can be externally averaged and used to control the gain of an ampliﬁer to close an AGC loop around the A/D con-

verter. This type of AGC sets the level based on the median value on the input.

System Clock. Asynchronous to the processor interface and serial inputs.

DESCRIPTION

COFSYNC

SOF

SOFSYNC

A2-0

C7-0

FZ_ST

FZ_CT

LKINT

I/O

THRESH

SLOCLK

ISER

QSER

SSYNC

SERCLK

AOUT9-0

BOUT9-0

SMBLCLK

OEA

OEB

HI/LO

CLK

3-255

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	HSP50210JC-52	HSP50210
Description	SPECIALTY TELECOM CIRCUIT, PQCC84	SPECIALTY TELECOM CIRCUIT, PQCC84

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