PRELIMINARY
MX98715A
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
1. FEATURES
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
• Fully comply to IEEE 802.3u specification
• Operates over 100 meters of STP and category 5
UTP cable
• Fully comply to PCI spec. 2.1 up to 33MHz
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.0
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.0
• Support full and half duplex operations in both 100
Base-TX and 10 Base-T mode
• Magic Packet
TM
mode to support Remote-Wake-Up
and Remote-Power-On
• 100/10 Base-T NWAY auto negotiation function
• Large on-chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers deliv-
ers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization, best fit in server and windows appli-
cation.
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 64K bytes boot ROM interface
• Three levels of loopback diagnositic capability
• Support a variety of flexible address filtering modes
with 16 CAM address and 512 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5V power supply, CMOS technology, 128-pin
PQFP package/LQPF package
( Magic Packet Technology is a trademark of Advanced
Micro Device Corp. )
2. GENERAL DESCRIPTIONS
The MX98715A controller is an IEEE802.3u compliant
single chip 32-bit full duplex, 10/100Mbps highly inte-
grated Fast Ethernet combo solution, designed to ad-
dress high performance local area networking (LAN)
system application requirements.
MX98715A's PCI bus master architecture delivers the
optimized performance for future high speed and pow-
erful processor technologies. In other words, the
MX98715A not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth uti-
lization. To further reduce maintenance costs the
MX98715A uses drivers that are backward compatible
with the original MXIC MX98713 series controllers.
The MX98715A contains a PCI local bus glueless inter-
face, a Direct Memory Access (DMA) buffer manage-
ment unit, an IEEE802.3u-compliant Media Access Con-
troller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98715A-based adapter allows a
single RJ-45 connector to link with the other IEEE802.3u-
P/N:PM0537
compliant device without re-configuration.
In MX98715A, an innovative and proprietary design
"Adaptive Network Throughput Control" (ANTC) is built-
in to configure itself automatically by MXIC's driver based
on the PCI burst throughput of different PCs. With this
proprietary design, MX98715A can always optimize its
operating bandwidth, network data integrity and through-
put for different PCs.
The MX98715A features Remote-Power-On and Re-
mote-Wake-Up capability and is compliant with the Ad-
vanced Configuration and Power Interface version 1.0
(ACPI). This support enables a wide range of wake-up
capabilities, including the ability to customize the con-
tent of specified packet which PC should be responded
to, even when it is in a low-power state. PCs and work-
stations could take advantage of these capabilities of
being waked up and served simultaneously over the net-
work by remote server or workstation. It helps organi-
zations reduce their maintenance cost of PC network.
The 32-bit multiplexed bus interface unit of MX98715A
provides a direct interface to a PCI local bus, simplifing
the design of an Ethernet adapter in a PC system. With
its on-chip support for both little and big endian byte
alignment, MX98715A can also address non-PC appli-
cations.
REV. 1.2, FEB. 24, 1999
1
MX98715A
4. PIN DESCRIPTION ( 128 PIN PQFP )
( T/S : tri-state, S/T/S : sustended tri-state, I : input, O : output, O/D : open drain )
Pin Name
AD[31:0]
Type
T/S
Pin No
116, 117
119,120,
122,124,
125,127,
3,4,6,7,9,
10,12,13,
26,28,29,
31-33,35,
36,38,39,
41,42,44,
45,47,48
128,14
25,37
128 Pin Function and Driver
PCI address/data bus: shared PCI address/data bus lines. Little or big endian
byte ordering are supported.
CBE[3:0]
T/S
FRAMEB
S/T/S 15
TRDYB
IRDYB
S/T/S 18
S/T/S 17
DEVSELB S/T/S 19
IDSEL
I
1
113
112
110
111
23
PCICLK
I
RSTB
I
LANWAKE O
INTAB
SERRB
PERRB
O/D
O/D
S/T/S 22
PCI command and byte enable bus: shared PCI command byte enable bus,
during the address phase of the transaction, these four bits provide the bus
command. During the data phase, these four bits provide the byte enable.
PCI FRAMEB signal: shared PCI cycle start signal, asserted to indicate the
beginning of a bus transaction. As long as FRAMEB is asserted, data
transfers continue.
PCI Target ready: issued by the target agent, a data phase is completed on
the rising edge of PCICLK when both IRDYB and TRDYB are asserted.
PCI Master ready: indicates the bus master's ability to complete the current
data phase of the transaction. A data phase is completed on any rising edge
of PCICLK when both IRDYB and TRDYB are asserted.
PCI slave device select: asserted by the target of the current bus access.
When 98715A is the initiator of current bus access, the target must assert
DEVSELB within 5 bus cycles, otherwise cycle is aborted.
PCI initialization device select: target specific device select signal for
configuration cycles issued by host.
PCI bus clock input: PCI bus clock range from 16MHz to 33MHz.
PCI bus reset: host system hardware reset.
Power Management Event:When high indicating a power management event
occures, such as detection of a Magic packet, a wake up frame, or link change.
PCI bus interrupt request signal: wired to INTAB line.
PCI bus system error signal: If an address parity error is detected and CFCS
bit 8 is enabled, SERRB and CFCS's bit 30 will be asserted.
PCI bus data error signal: As a bus master, when a data parity error is
detected and CFCS bit 8 is enabled, CFCS bit 24 and CSR5 bit 13 will be
asserted. As a bus target, a data parity error will cause PERRB to be
asserted.
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REV. 1.2, FEB. 24, 1999
3
MX98715A
Pin Name
PAR
STOPB
REQB
GNTB
BPA1
(EEDI)
BPA0
(EECK)
BPA[15:0]
O
78-76,
73-70,
68-60
58
Type
T/S
Pin No
24
128 Pin Function and Driver
PCI bus parity bit: shared PCI bus even parity bit for 32 bits AD bus and CBE
bus.
PCI Target requested transfer stop signal: as bus master, assertion of STOPB
cause MX98715A either to retry, disconnect, or abort.
PCI bus request signal: to initiate a bus master cycle request
PCI bus grant acknowledge signal: host asserts to inform MX98715A that
access to the bus is granted
Boot PROM address bit 1(EECS=0): together with BPA[15:0] to access
external boot PROM up to 256KB.
EEPROM data in(EECS=1): EEPROM serial data input pin.
Boot PROM address bit 0(EECS=0): together with BPA[15:0] to access
external boot PROM up to 256KB.
EEPROM clock(EECS=1): EEPROM clock input pin
Boot PROM address line.
Boot PROM data line 0(EECS=0): boot PROM or flash data line 0.
EEPROM data out(EECS=1): EEPROM serial data outpin(during reset
initialization).
Boot PROM data lines: boot PROM or flash data lines 7-0.
EEPROM Chip Select pin.
Boot PROM Output Enable.
Connecting an external resistor to ground, Resistor value=510 ohms
Connecting an external resistor to ground, Resistor value=510 ohms
No connection.
No Connection.
Twisted pair receive differential input: Support both 10 Base-T and 100
Base-TX receive differential input.
Twisted pair receive differential input: Support both 10 Base-T and 100
Base-TX receive differential input
Twisted pair transmit differential output: Support both 10 Base-T and 100
Base-TX transmit differential output
Twisted pair transmit differential output: Support both 10 Base-T and 100
Base-TX transmit differential output
Reference clock: 25MHz oscillator clock input
Programmable LED pin 0:
CSR9.28=1 Set the LED as Link Speed (10/100) LED.
CSR9.28=0 Set the LED as Activity LED.
Default is activity LED after reset.
S/T/S 20
T/S
I
O
115
114
61
O
60
BPD0
(EEDO)
BPD[7:0]
EECS
BOEB
RDA
RTX
RTX2EQ
NC
RXIP
RXIN
TXOP
TXON
CKREF
LED0
T/S
T/S
O
O
O
O
O
I
I
I
O
O
I
O
51-58
59
69
83
102
101
100
92
91
98
97
85
79
P/N:PM0537
REV. 1.2, FEB. 24, 1999
4
Analog electronics
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