Integrated
Circuit
Systems, Inc.
ICS9250-29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Solano type chipset.
Output Features:
•
2 CPU (2.5V) (up to 133MHz achievable through I
2
C)
•
13 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
•
5 PCI (3.3 V) @33.3MHz
•
1 IOAPIC (2.5V) @ 33.3 MHz
•
3 Hublink clocks (3.3 V) @ 66.6 MHz
•
2 (3.3V) @ 48 MHz (Non spread spectrum)
•
1 REF (3.3V) @ 14.318 MHz
Features:
•
Supports spread spectrum modulation,
0 to -0.5% down spread.
•
I
2
C support for power management
•
Efficient power management scheme through PD#
•
Uses external 14.138 MHz crystal
•
Alternate frequency selections available through I
2
C
control.
IOAPIC
VDDL
GNDL
*FS1/REF
VDDR
X1
X2
GNDR
VDD3
3V66-0
3V66-1
3V66-2
GND3
PCICLK0
PCICLK1
PCICLK2
VDD2
GND2
PCICLK3
PCICLK4
FS0
GNDA
VDDA
SCLK
SDATA
GNDF
VDDF
48MHz_0
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GNDL
VDDL
CPUCLK0
CPUCLK1
GND1
SDRAM0
SDRAM1
VDD1
GND1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD1
GND1
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDD1
GND1
SDRAM10
SDRAM11
VDD1
GND1
SDRAM12
TRISTATE#/PD#**
48MHz_1
56-Pin 300mil SSOP
* This input has a 50K pull-down to GND.
** This input has a 50K pull-up to VDD
9
9
Block Diagram
Functionality
Tristate#
FS0
0
1
0
1
0
1
FS1
X
X
0
0
1
1
CPU
MHz
Tristate
Test
66MHz
100MHz
133MHz
133MHz
SDRAM
MHz
Tristate
Test
100MHz
100MHz
133MHz
100MHz
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
/2
/3
REF
VDDL
2
CPU66/100/133 [1:0]
3V66 [2:0]
SDRAM [12:0]
PCICLK [4:0]
IOAPIC
VDDL
0
0
1
1
1
1
FS(1:0)
PD#
TRISTATE#
SDATA
SCLK
Control
Logic
Config
Reg
/2
/2
3
13
5
Power Groups
VDDA, GNDA = CPU, PLL (analog)
VDDF, GNDF = Fixed PLL, 48M (analog/digital)
VDDR, GNDR = REF, X1, X2 (analog/digital)
VDD3, GND3 = 3V66 (digital)
VDD2, GND2 = PCI (digital)
VDD1, GND1 = SDRAM (digital)
VDDL, GNDL = IOAPIC, CPU (digital)
PLL2
2
48MHz [1:0]
9250-29 Rev A 02/01/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
ICS9250-29
ICS9250-29
General Description
The
ICS9250-29
is a single chip clock solution for Solano type chipset. It provides all necessary clock signals for such
a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-29
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Pin Configuration
PIN NUMBER
1
2, 55
3, 56
4
5, 9, 17, 23, 27,
33, 37, 43, 49
6
7
P I N NA M E
IOAPIC
VDDL
GNDL
FS1
REF
VDDx
X1
X2
TYPE
OUT
PWR
PWR
IN
OUT
PWR
IN
OUT
PWR
OUT
IN
OUT
IN
DESCRIPTION
2.5V clock output running at 33.3MHz.
2.5V power supply for CPU & IOAPIC
Ground for 2.5V power supply for CPU & IOAPIC
Function Select pin. Determines CPU frequency, all output functionality
3.3V, 14.318MHz reference clock output.
3.3V power supply
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Ground pins for 3.3V supply
3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B
Function Select pin. Determines CPU frequency, all output functionality.
3.3V PCI clock outputs
At power up the TRISTATE#/PD# pin defaults to the TRISTATE#
input function to enable the TRISTATE# and TEST modes. (see Shared
Pin Operation for full description).
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
Clock input of I
2
C input
Data input for I
2
C serial input.
3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s .
3.3V output running 100MHz and 133MHz. All SDRAM outputs can
be turned off through I
2
C
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS pins.
8, 13, 18, 22, 26,
GNDx
32, 36, 42, 48, 52
12, 11, 10
21
3V66 (2:0)
FS0
20, 19, 16, 15, 14 PCICLK (4:0)
TRISTATE#
30
PD#
24
25
29, 28
SCLK
SDATA
48MHz (1:0)
IN
IN
IN
OUT
OUT
OUT
31, 34, 35, 38,
SD
39, 40, 41, 44, [12RAM
:0]
45, 46, 47, 50, 51
53, 54
CPUCLK (1:0)
2
ICS9250-29
Power Down Waveform
Note
1.
After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the
output clocks are driven Low on their next High to Low tranistiion.
2.
Power-up latency <3ms.
3.
Waveform shown for 100MHz
Maximum Allowed Current
Solano
Condition
Powerdown Mode
(PWRDWN# = 0)
Full Active 66MHz
FS(1:0) = 00
Full Active 100MHz
FS(1:0) = 01
Full Active 133MHz
FS(1:0) = 11
Full Active 133MHz
FS(1:0) = 10
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
All static inputs = Vddq3 or GND
2mA
35mA
50mA
60mA
60mA
Max 3.3V supply consumption
Max discrete cap loads,
Vddq3 = 3.465V
All static inputs = Vddq3 or GND
2mA
440mA
430mA
440mA
500mA
Clock Enable Configuration
PD#
0
1
CPUCLK
LOW
ON
SDRAM
LOW
ON
IOAPIC
LOW
ON
3V66
LOW
ON
PCICLK
LOW
ON
REF,
48MHz
LOW
ON
Osc
OFF
ON
VCOs
OFF
ON
3
ICS9250-29
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0) through byte 5
ICS clock will
acknowledge
each byte
one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Note:
This clock does not support Read Back. Doing a
read back will lock up the PIIX-4 system.
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C (SMB) component. It is only a "write" mode SMB device, no readback on
this part.
Read-Back will lock up the PIIX-4 due to the Byte count of 00
H
.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The
data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
4
ICS9250-29
Truth Table
Tristate
0
0
1
1
1
1
FS0
0
1
0
1
0
1
FS1
X
X
0
0
1
1
CPU
Tristate
TCLK/2
66.6 MHz
100 MHz
133 MHz
133 MHz
SDRAM
Tristate
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
3V66
Tristate
TCLK/3
66.6 MHz
66.6 MHz
66.6 MHz
66.6 MHz
PCI
Tristate
TCLK/6
33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
Tristate
TCLK
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
IOAPIC
Tristate
TCLK/6
33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
-
-
29
28
-
Name
(Reserved ID)
(Reserved ID)
(Reserved ID)
(Reserved ID)
Spread Spectrum
48MHz_1
48MHz_0
(Reserved ID)
PWD
0
0
0
1
0
1
1
0
Description
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(1=On / 0=Off )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
Note:
Reserved ID bits must be written with "0"
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
40
41
44
45
46
47
50
51
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
PWD
1
1
1
1
1
1
1
1
Description
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
5
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