LTC1873
Dual 550kHz Synchronous
2-Phase Switching Regulator
Controller with 5-Bit VID
FEATURES
s
s
DESCRIPTIO
s
s
s
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s
s
s
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Two Independent PWM Controllers in One Package
Side 1 Output Is Compliant with Intel Desktop
VRM 8.4 Specifications (Includes 5-Bit VID DAC)
1.3V to 3.5V Output Voltage with 50mV/100mV Steps
Two Sides Run Out-of-Phase to Minimize C
IN
All N-Channel External MOSFET Architecture
No External Current Sense Resistors Required
Precison Internal 0.8V
±1%
Reference
550kHz Switching Frequency Minimizes External
Component Size
Very Fast Transient Response
Up to 25A Output Current per Channel
Low Shutdown Current: < 100µA
Small 28-Pin SSOP Package
APPLICATIO S
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Microprocessor Core and I/O Supplies
Multiple Logic Supply Generator
High Efficiency Power Conversion
Chipset Power Supply
The LTC
®
1873 is a dual switching regulator controller opti-
mized for high efficiency with low input voltages. It includes
two complete, on-chip, independent switching regulator con-
trollers. Each is designed to drive a pair of external
N-channel MOSFETs in a voltage mode feedback, synchro-
nous buck configuration. The LTC1873 includes digital out-
put voltage adjustment on side 1 that conforms to the Intel
Desktop VID specification. A constant-frequency, true PWM
design minimizes external component size and cost and
optimizes load transient performance. The synchronous buck
architecture automatically shifts to discontinuous and then to
Burst Mode
TM
operation as the output load decreases, ensur-
ing maximum efficiency over a wide range of load currents.
The LTC1873 features an onboard reference trimmed to 1%
and delivers better than 1.5% regulation at the converter
outputs over all combinations of line, load and temperature.
Each channel can be enabled independently; with both chan-
nels disabled, the LTC1873 shuts down and supply current
drops below 100µA.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
4.5V TO 5.5V
Low Cost Desktop CPU Supply with RDRAM Keepalive
+
10Ω
4.75k
0.1%
330pF
C
IN
MBR0530T
10µF
V
CC
FB2
56pF
COMP2
1k
QSS1
STBY/ON
1k
QSS2
0.1µF
SENSE
220pF
FB1
39pF
COMP1
FCB
5-BIT VID
VID4:0
SGND
RUN/SS2
RUN/SS1
PV
CC
BOOST2
TG2
SW2
BG2
I
MAX2
MBR0530T
QT1B
TG1
SW1
BG1
33k
I
MAX1
PGND
QB1B
QB1A
QT1A
1µF
L1
V
CORE
1.3V TO 3.5V
20A
C
OUT1
C
IN
= SANYO 10MV1200GX (6 IN PARALLEL)
C
OUT1
= SANYO 6MV1500GX (8 IN PARALLEL)
C
OUT2
= SANYO 6MV1500GX (3 IN PARALLEL)
L1: 1µH SUMIDA CEP125-1R0MC-H
L2: 2.2µH COILTRONICS UP2B-2R2
QSS1, QSS2: MOTOROLA MMBT3904LT1
QT1A, QT1B, QB1A, QB1B: FAIRCHILD FDS6670A
QT2, QB2: 1/2 SILICONIX Si4966
BOOST1
47k
QB2
QT2
1µF
L2
16.9k
0.1%
V
RDRAM
2.5V/7A
2.45V/100mA STANDBY
C
OUT2
IN
1µF
OUT
16.2k
0.1%
LT1761
GND ADJ
+
10k
0.1%
68k
LTC1873 FAULT
56k
U
+
+
1873 TA01
U
U
1
LTC1873
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
PV
CC
BOOST1
BG1
TG1
SW1
I
MAX1
FCB
RUN/SS1
COMP1
1
2
3
4
5
6
7
8
9
28 I
MAX2
27 BOOST2
26 BG2
25 TG2
24 SW2
23 PGND
22 FAULT
21 RUN/SS2
20 COMP2
19 FB2
18 V
CC
17 VID4
16 VID3
15 VID2
G PACKAGE
28-LEAD PLASTIC SSOP
T
JMAX
= 125°C,
θ
JA
= 55°C/ W
Supply Voltage
V
CC ...........................................................................................
7V
BOOSTn
...............................................................
15V
BOOSTn – SWn .................................................... 7V
Input Voltage
SWn .......................................................... – 1V to 8V
VIDn ....................................................... – 0.3V to 7V
All Other Inputs ......................... – 0.3V to V
CC
+ 0.3V
Peak Output Current < 10µs
TGn, BGn ............................................................... 5A
Operating Temperature Range
(Note 2) ............................................. – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1873EG
SGND 10
FB1 11
SENSE 12
VID0 13
VID1 14
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
V
CC
= 5V unless otherwise specified. (Note 4)
SYMBOL
V
CC
PV
CC
BV
CC
I
CC
IPV
CC
I
BOOST
V
FB
∆V
FB
I
FB
V
FCB
∆V
FCB
I
FCB
V
RUN
I
SS
PARAMETER
V
CC
Supply Voltage
PV
CC
Supply Voltage
BOOST Pin Voltage
V
CC
Supply Current
PV
CC
Supply Current
BOOST Pin Current
Feedback Voltage
Feedback Voltage Line Regulation
Feedback Current
FCB Threshold
FCB Feedback Hysteresis
FCB Pin Current
RUN/SS Pin RUN Threshold
Soft Start Source Current
RUN/SSn = 0V
q
q
CONDITIONS
q
MIN
3
3
2.7
TYP
MAX
7
7
7
UNITS
V
V
V
mA
µA
mA
µA
mA
µA
V
%/V
µA
V
mV
µA
V
µA
Main Control Loop
(Note 3)
V
BOOST
– V
SW
(Note 3)
Test Circuit 1
RUN/SS1 = RUN/SS2 = 0V (Note 6)
Test Circuit 1 (Note 5)
RUN/SS1 = RUN/SS2 = 0V (Note 6)
Test Circuit 1 (Note 5)
RUN/SS1 = RUN/SS2 = 0V
Test Circuit 1
V
CC
= 3V to 7V
FB2 Only (Note 7)
q
q
q
q
q
q
q
q
q
q
q
q
2.2
30
2.2
6
1.3
0.1
0.790
0.800
±0.005
±0.001
0.75
0.8
20
±0.001
0.45
– 1.5
0.55
– 3.5
8
100
6
100
3
10
0.810
±0.05
±1
0.85
±1
0.65
– 5.5
2
U
W
U
U
W W
W
LTC1873
ELECTRICAL CHARACTERISTICS
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
V
CC
= 5V unless otherwise specified. (Note 4)
SYMBOL
V
OSC
f
OSC
Φ
OSC2
DC
MIN1
DC
MIN2
DC
MAX
t
NOV
t
r
, t
f
A
VFB
GBW
I
ERR
V
MIN
V
MAX
A
VILIM
I
IMAX
Status Outputs
V
FAULT
V
OLF
I
FAULT
t
FAULT
VID Inputs
R1
R
PULLUP
VID
T
I
VID-LEAK
V
PULLUP
Resistance Between SENSE and FB1
VID Input Pull-Up Resistance
VID Input Voltage Threshold
VID Input Leakage Current
VID Pull-Up Voltage
Side 1 Only
Programmed from 1.3V to 3.5V
V
DIODE
= 0.6V (Note 8)
V
IL
(2.7V
≤
V
CC
≤
5.5V)
V
IH
(2.7V
≤
V
CC
≤
5.5V)
V
CC
< VID < 7V (Note 8)
V
CC
= 3.3V
V
CC
= 5V
1.6
0.01
2.8
4.5
±1
q
PARAMETER
Oscillator Amplitude
Oscillator Frequency
Controller 2 Oscillator Phase
Minimum Duty Cycle
Minimum Duty Cycle
Maximum Duty Cycle
Driver Nonoverlap
Driver Rise/Fall Time
FB DC Gain
FB Gain Bandwidth
FB Sink/Source Current
MIN Comparator Threshold
MAX Comparator Threshold
I
LIM
Gain
I
MAX
Source Current
FAULT Trip Point
FAULT Output Low Voltage
FAULT Output Current
FAULT Delay Time
CONDITIONS
MIN
TYP
1
MAX
UNITS
V
P-P
Switching Characteristics
Test Circuit 1
Relative to Controller 1
V
FB
< V
MAX
V
FB
> V
MAX
Test Circuit 1 (Note 9)
Test Circuit 1 (Note 9)
q
q
q
q
q
q
475
7
0
87
550
180
10
90
40
12
750
kHz
DEG
%
%
93
100
80
%
ns
ns
dB
MHz
mA
Feedback Amplifier
q
74
±3
815
85
25
±10
760
840
40
785
COMP
N
Output
q
q
q
mV
mV
dB
Current Limit Loop
I
MAX
= 0V
V
FB
Relative to Regulated V
OUT
I
FAULT
= 1mA
V
FAULT
= 0V
V
FB
> V
FAULT
to FAULT
(Note 9)
q
q
q
–7
+ 10
–10
+ 15
0.03
– 10
25
20
–14
+ 20
0.1
µA
%
V
µA
µs
kΩ
V
OUT
Error % Output Voltage Accuracy
– 1.5
40
1.5
0.4
%
kΩ
V
V
µA
V
V
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
The LTC1873 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3:
PV
CC
and BV
CC
(V
BOOST
– V
SW
) must be greater than V
GS(ON)
of
the external MOSFETs used to ensure proper operation.
Note 4:
All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 5:
Supply current in normal operation is dominated by the current
needed to charge and discharge the external MOSFET gates. This current
will vary with supply voltage and the external MOSFETs used.
Note 6:
Supply current in shutdown is dominated by external MOSFET
leakage and may be significantly higher than the quiescent current drawn
by the LTC1873, especially at elevated temperature.
Note 7:
Feedback current at FB1 will be higher due to internal VID
resistors.
Note 8:
Each built-in pull-up resistor attached to the VID inputs also has a
series diode connected to V
CC
to allow input voltages higher than the V
CC
supply without damage or clamping. (See Block Diagram.)
Note 9:
Rise and fall times are measured at 20% to 80% levels. Delay and
nonoverlap times are measured using 50% levels.
3
LTC1873
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
100
V
IN
= 5V
V
OUT
= 3.3V
V
OUT
= 2.5V
V
OUT
= 1.6V
EFFICIENCY (%)
90
DRIVER SUPPLY CURRENT (mA)
80
70
0
5
10
LOAD CURRENT (A)
15
1873 G01
Supply Current vs Temperature
2.6
TEST CIRCUIT 1
2.4 C
L
= 0pF
SUPPLY CURRENT (mA)
PV
CC
FREQUENCY DRIFT (%)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
– 50 – 25
0
BOOST1, BOOST2
V
CC
0
–0.5
–1.0
–1.5
–2.0
R
ON
(Ω)
75
50
25
TEMPERATURE (°C)
RUN/SS Source Current
vs Temperature
5.0
4.5
NONOVERLAP TIME (ns)
V
CC
= 5V
SOURCE CURRENT (µA)
4.0
3.5
3.0
2.5
2.0
–50 –25
RISE/FALL TIME (ns)
50
25
75
0
TEMPERATURE (°C)
4
U W
100
1873 G04
Transient Response
V
IN
= 5V
V
OUT
= 1.8V
I
LOAD
= 0A-10A-0A
±2.2%
MAX DEVIATION
35
MOSFET Driver Supply Current
vs Gate Capacitance
TEST CIRCUIT 1
ONE DRIVER LOADED
30 MULTIPLY BY # OF ACTIVE
DRIVERS TO OBTAIN TOTAL
25 DRIVER SUPPLY CURRENT
20mV/
DIV
20
15
10
5
0
10µs/DIV
1873 G02
0
2000
4000
6000
8000
GATE CAPACITANCE (pF)
10000
1873 G03
Frequency Drift vs Temperature
2.5
2.0
1.5
1.0
0.5
V
CC
= 5V
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
50
25
0
75
TEMPERATURE (°C)
100
125
Driver R
ON
vs Temperature
V
PVCC
= 5V
V
BOOST
– V
SW
= 5V
125
–2.5
–50 –25
0.4
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
1873 G05
1873 G06
Nonoverlap Time vs Temperature
70
60
50
40
30
20
10
0
–50 –25
BG FALLING EDGE
TG RISING EDGE
TEST CIRCUIT 1
C
L
= 2000pF
TG FALLING EDGE
BG RISING EDGE
15
Driver Rise/Fall vs Temperature
TEST CIRCUIT 1
C
L
= 2000pF
14
13
12
11
100
125
50
25
75
0
TEMPERATURE (°C)
100
125
12
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
1873 G07
1873 G08
1873 G09
LTC1873
PI FU CTIO S
PV
CC
(Pin 1):
Driver Power Supply Input. PV
CC
provides
power to the two BGn output drivers. PV
CC
must be
connected to a voltage high enough to fully turn on the
external MOSFETs QB1 and QB2. PV
CC
should generally
be connected directly to V
IN
. PV
CC
requires at least a 1µF
bypass capacitor directly to PGND.
BOOST1 (Pin 2):
Controller 1 Top Gate Driver Supply. The
BOOST1 pin supplies power to the floating TG1 driver.
BOOST1 should be bypassed to SW1 with a 1µF capacitor.
An additional Schottky diode from V
IN
to BOOST1 pin will
create a complete floating charge-pumped supply at
BOOST1. No other external supplies are required.
BG1 (Pin 3):
Controller 1 Bottom Gate Drive. The BG1 pin
drives the gate of the bottom N-channel synchronous
switch MOSFET, QB1. BG1 is designed to drive up to
10,000pF of gate capacitance directly. If RUN/SS1 goes
low, BG1 will go low, turning off QB1. If FAULT mode is
tripped, BG1 will go high and stay high, keeping QB1 on
until the power is cycled.
TG1 (Pin 4):
Controller 1 Top Gate Drive. The TG1 pin
drives the gate of the top N-channel MOSFET, QT1. The
TG1 driver draws power from the BOOST1 pin and returns
to the SW1 pin, providing true floating drive to QT1. TG1
is designed to drive up to 10,000pF of gate capacitance
directly. In shutdown or fault modes, TG1 will go low.
SW1 (Pin 5):
Controller 1 Switching Node. SW1 should be
connected to the switching node of converter 1. The TG1
driver ground returns to SW1, providing floating gate
drive to the top N-channel MOSFET switch, QT1. The
voltage at SW1 is compared to I
MAX1
by the current limit
comparator while the bottom MOSFET, QB1, is on.
I
MAX1
(Pin 6):
Controller 1 Current Limit Set. The I
MAX1
pin sets the current limit comparator threshold for
controller 1. If the voltage drop across the bottom MOSFET,
QB1, exceeds the magnitude of the voltage at I
MAX1
,
controller 1 will go into current limit. The I
MAX1
pin has an
internal 10µA current source pull-up, allowing the current
threshold to be set with a single external resistor to PGND.
This current setting resistor should be Kelvin connected to
the source of QB1. See the Current Limit Programming
section for more information on choosing R
IMAX
.
FCB (Pin 7):
Force Continuous Bar. The FCB pin forces
both converters to maintain continuous synchronous
operation regardless of load when the voltage at FCB
drops below 0.8V. FCB is normally tied to V
CC
. To force
continuous operation, tie FCB to SGND. FCB can also be
connected to a feedback resistor divider from a secondary
winding on one converter’s inductor to generate a third
regulated output voltage. Do not leave FCB floating.
RUN/SS1 (Pin 8):
Controller 1 Run/Soft-Start. Pulling
RUN/SS1 to SGND will disable controller 1 and turn off
both of its external MOSFET switches. Pulling both
RUN/SS pins down will shut down the entire LTC1873,
dropping the quiescent supply current below 50µA. A
capacitor from RUN/SS1 to SGND will control the turn-on
time and rate of rise of the controller 1 output voltage at
power-up. An internal 3.5µA current source pull-up at
RUN/SS1 pin sets the turn-on time at approximately
50ms/µF.
COMP1 (Pin 9):
Controller 1 Loop Compensation. The
COMP1 pin is connected directly to the output of the first
controller’s error amplifier and the input to the PWM
comparator. An RC network is used at the COMP1 pin to
compensate the feedback loop for optimum transient
response.
SGND (Pin 10):
Signal Ground. All internal low power
circuitry returns to the SGND pin. Connect to a low
impedance ground, separated from the PGND node. All
feedback, compensation and soft-start connections should
return to SGND. SGND and PGND should connect only at
a single point, near the PGND pin and the negative plate of
the C
IN
bypass capacitor.
FB1 (Pin 11):
Controller 1 Feedback Input. The loop
compensation network for controller 1 should be con-
nected to FB1. FB1 is connected internally to the VID
resistor network to set the output voltage at side 1.
SENSE (Pin 12):
Output Sense. Connect to V
OUT1
.
VID0 to VID4 (Pins 13 to 17):
VID Programming Inputs.
These are logic inputs that set the output voltage at side 1
to a preprogrammed value (see Table 1). VID4 is the MSB,
VID0 is the LSB. The codes selected by the VIDn inputs
correspond to the Intel Desktop VID specification. Each
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