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843004AGLF

Description
TSSOP-24, Tube
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size351KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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843004AGLF Overview

TSSOP-24, Tube

843004AGLF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP-24
Contacts24
Manufacturer packaging codePGG24
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length7.8 mm
Humidity sensitivity level1
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-30 °C
Maximum output clock frequency680 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency26.5625 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate135 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
FemtoClocks™ LVCMOS/Crystal-to-3.3V
LVPECL Frequency Synthesizer
843004
DATA SHEET
General Description
The 843004 is a 4 output LVPECL synthesizer optimized to
generate Fibre Channel reference clock frequencies and is a
member of the HiPerClocks
TM
family of high performance clock
solutions from IDT. Using a 26.5625MHz 18pF parallel resonant
crystal, the following frequencies can be generated based on the 2
frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz,
159.375MHz, 156.25, 106.25MHz, and 53.125MHz. The 843004
uses IDT’s 3
rd
generation low phase noise VCO technology and
can achieve 1ps or lower typical rms phase jitter, easily meeting
Fibre Channel jitter requirements. The 843004 is packaged in a
small 24-pin TSSOP package.
Features
Four 3.3Vdifferential LVPECL output pairs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended clock input
Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
VCO range: 560MHz – 680MHz
RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz – 10MHz): 0.72ps (typical)
Offset
Noise Power
100Hz ................ -95.0 dBc/Hz
1kHz .................. -114.3 dBc/Hz
10kHz ................ -123.8 dBc/Hz
100kHz .............. -124.6 dBc/Hz
Table 3A. Bank A Frequency Table
Inputs
Input Frequency (MHz)
26.5625
26.5625
26.5625
26.5625
26.04166
23.4375
F_SEL1
0
0
1
1
0
0
F_SEL0
0
1
0
1
1
0
M Div. Value
24
24
24
24
24
24
Full 3.3V supply mode
-30°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
N Div. Value
3
4
6
12
4
3
M/N Div. Value
8
6
4
2
6
8
Output Frequency (MHz)
212.5
159.375
106.25
53.125
156.25
187.5
Block Diagram
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
2
Q0
1
nQ0
Q1
nQ1
Pin Assignment
nQ1
Q1
V
CCO
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
F_SEL0
V
CC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
CCO
Q3
nQ3
V
EE
nc
nXTAL_SEL
TEST_CLK
V
EE
XTAL_IN
XTAL_OUT
TEST_CLK
Pulldown
26.5625MHz
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
0
Q2
nQ2
ICS843004
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
©2015 Integrated Device Technology, Inc.
M = 24 (fixed)
Q3
nQ3
MR
Pulldown
843004 Rev C 5/26/15
1

843004AGLF Related Products

843004AGLF 843004AGLFT
Description TSSOP-24, Tube TSSOP-24, Reel
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction TSSOP-24 TSSOP-24
Contacts 24 24
Manufacturer packaging code PGG24 PGG24
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
JESD-30 code R-PDSO-G24 R-PDSO-G24
JESD-609 code e3 e3
length 7.8 mm 7.8 mm
Humidity sensitivity level 1 1
Number of terminals 24 24
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -30 °C -30 °C
Maximum output clock frequency 680 MHz 680 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP24,.25 TSSOP24,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260
power supply 3.3 V 3.3 V
Master clock/crystal nominal frequency 26.5625 MHz 26.5625 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm
Maximum slew rate 135 mA 135 mA
Maximum supply voltage 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level OTHER OTHER
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
width 4.4 mm 4.4 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
Base Number Matches 1 1
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