a
Dual Channel, 12-Bit 105 MSPS IF Sampling
A/D Converter with Analog Input
Signal Conditioning
AD10200
includes two wide-dynamic range ADCs. Each ADC has a
transformer coupled front-end optimized for Direct-IF sampling.
The AD10200 has on-chip track-and-hold circuitry, and utilizes
an innovative architecture to achieve 12-bit, 105 MSPS perfor-
mance. The AD10200 uses innovative high-density circuit
design to achieve exceptional matching and performance while
still maintaining excellent isolation, and providing for significant
board area savings.
The AD10200 operates with 5.0 V supply for the analog-to-
digital conversion. Each channel is completely independent
allowing operation with independent encode and analog inputs.
The AD10200 is packaged in a 68-lead ceramic chip carrier
package. Manufacturing is done on Analog Devices, Inc. MIL-
38534 Qualified Manufacturers Line (QML) and components
are available up to Class-H (–55°C to +125°C).
PRODUCT HIGHLIGHTS
FEATURES
Dual, 105 MSPS Minimum Sample Rate
Channel-Channel Isolation, >80 dB
AC-Coupled Signal Conditioning Included
Gain Flatness up to Nyquist: < 0.2 dB
Input VSWR 1.1:1 to Nyquist
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
0.850 W per Channel
Industrial and Military Grade
APPLICATIONS
Radar IF Receivers
Phased Array Receivers
Communications Receivers
Secure Communications
GPS Antijamming Receivers
Multichannel, Multimode Receivers
PRODUCT DESCRIPTION
1. Guaranteed sample rate of 105 MSPS.
2. Input signal conditioning with full power bandwidth to
250 MHz.
3. Fully tested/characterized performance at 121 MHz A
IN
.
4. Optimized for IF sampling.
The AD10200 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
FUNCTIONAL BLOCK DIAGRAM
A
IN
A2
7
A
IN
B2
63
D00A
34
(LSB)
D01A
33
T1A
D02A
32
D03A
31
D04A
30
D05A
29
D06A
28
D07A
25
D08A
24
D09A
23
D10A
22
D11A
21
(MSB)
TIMING
REF
REF
TIMING
OUTPUT RESISTORS
OUTPUT RESISTORS
12
ADC
12
ADC
12
12
T/H
50
50
T1B
50
D00B
(LSB)
49
D01B
48
D02B
47
D03B
46
D04B
AD10200
T/H
45
D05B
42
D06B
41
D07B
40
D08B
39
D09B
38
D10B
37
D11B
(MSB)
18
17
3
56
53
54
ENCODEA
ENCODEA
REF_A_OUT
REF_B_OUT
ENCODEB
ENCODEB
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD10200–SPECIFICATIONS
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
Gain Error
2
Output Offset
ANALOG INPUT
Input Voltage Range
Input Impedance
Input VSWR
3
Analog Input Bandwidth, High
Analog Input Bandwidth, Low
ANALOG REFERENCE
Output Voltage
Load Current
Tempco
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Duty Cycle
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
Output Valid Time (t
V
)
4
Output Propagation Delay (
PD
)
4
Output Rise Time (t
R
)
Output Fall Time (t
F
)
DIGITAL INPUTS
Encode Input Common Mode
Differential Input (Enc,
Enc)
Logic “1” Voltage
Logic “0” Voltage
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
Logic “1” Voltage
4
Logic “0” Voltage
4
Output Coding
POWER SUPPLY
5
Power Dissipation
6
Power Supply Rejection Ratio
I (DV
DD
) Current
I (AV
CC
) Current
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
7
(Without Harmonics)
f
IN
= 10 MHz
f
IN
= 41 MHz
f
IN
= 71 MHz
f
IN
= 121 MHz
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
25°C
Full
Full
Temp
1
(V
DD
= 3.3 V, V
CC
= 5.0 V; ENCODE = 105 MSPS, unless otherwise noted)
Test
Level
MIL
Subgroup
Min
Typ
12
IV
IV
I
I
I
V
V
IV
IV
IV
I
V
V
I
IV
IV
V
V
IV
IV
V
V
IV
IV
IV
IV
IV
V
VI
VI
12
12
1, 2, 3
1, 2, 3
1, 2, 3
–0.99
–3
–9
–12
±
0.5
±
0.75
Guaranteed
±
1
+0.99
+3
+9
+12
Max
Unit
Bits
LSB
LSB
% FS
LSB
V p-p
Ω
Ratio
MHz
MHz
V
mA
ppm/°C
MSPS
MSPS
%
ns
ps rms
ns
ns
ns
ns
V
V
V
V
kΩ
pF
V
V
12
12
12
1, 2, 3
200
1
2.4
2.048
50
1.1:1
250
1.25:1
2.5
5
50
2.6
4, 5, 6
12
12
105
45
50
1.0
0.25
5.3
5.5
3.5
3.3
1.6
10
55
12
12
12
12
12
12
12
12
12
3.0
4.5
8.0
1.2
0.4
2.0
3
2.0
5.0
0.8
8
5
4.5
1, 2, 3
1, 2, 3
3.1
3.3
0
0.2
Two’s Complement
1800
±
0.5
25
340
2200
±
5
40
410
Full
Full
Full
Full
I
IV
I
I
1, 2, 3
12
1, 2, 3
1, 2, 3
mW
mV/V
mA
mA
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
V
I
II
I
II
I
II
4
5, 6
4
5, 6
4
5, 6
64
62
62.5
61.5
61
61
67
66
66.5
65
66.4
64
65
64
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
–2–
REV. A
AD10200
Parameter
DYNAMIC PERFORMANCE
(Continued)
Signal-to-Noise Ratio (SINAD)
8
(With Harmonics)
f
IN
= 10 MHz
f
IN
= 41 MHz
f
IN
= 71 MHz
f
IN
= 121 MHz
Spurious Free Dynamic Range
9
f
IN
= 10 MHz
f
IN
= 41 MHz
f
IN
= 71 MHz
f
IN
= 121 MHz
Two-Tone Intermodulation
Distortion
10
(IMD)
f
IN
= 10 MHz; f
IN
= 12 MHz
f
IN
= 71 MHz; f
IN
= 72 MHz
f
IN
= 121 MHz; f
IN
= 122 MHz
Channel-to-Channel Isolation
11
f
IN
= 121 MHz
Temp
Test
Level
MIL
Subgroup
Min
Typ
Max
Unit
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
V
I
II
I
II
I
II
V
V
I
II
I
II
I
II
4
5, 6
4
5, 6
4
5, 6
63
60.5
61
57
56
53
66
63
65.5
63
63.5
60
58.5
55
81
70
81
74
65
58
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
4
5, 6
4
5, 6
4
5, 6
73
67.5
67
60
61
55.5
25°C
Full
25°C
Full
25°C
Full
Full
V
V
V
V
I
II
IV
4
5, 6
12
55.5
53
80
86
81
70
65
62
57
85
dBc
dBc
dBc
dBc
dBc
dBc
dB
NOTES
1
All ac specifications tested by driving ENCODE and
ENCODE
differentially.
2
Gain Error measured at 2.5 MHz.
3
Input VSWR guaranteed 10 MHz to 200 MHz.
4
t
V
and t
PD
are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is
not to exceed an ac load of 10 pF or a dc current of
±
40 mA.
5
Supply voltages should remain stable within
±
5% for normal operation.
6
Power dissipation measured with encode at rated speed and 0 dBm analog input.
7
Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonic removed). Encode = 105 MSPS. SNR
is reported in dBFS, related back to converter full scale.
8
Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 105 MSPS. SINAD
is reported in dBFS, related back to converter full scale.
9
Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10
Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = x MHz
±
100 kHz, f2 = x MHz
±
100 kHz.
11
Channel-to-Channel isolation tested with A Channel/50
Ω
terminated (A
IN
A2) grounded and a full-scale signal applied to B Channel (A
IN
B2).
Specifications subject to change without notice.
REV. A
–3–
AD10200
ABSOLUTE MAXIMUM RATINGS
1, 2
Table I. Output Coding (VREF = 2.5 V) (Two’s Complement)
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . 5 V p-p(18 dBm)
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to V
DD
+ 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
2
Typical thermal impedances for “Z” package:
θ
JC
= 2.22°C/W;
θ
JA
= 24.3°C/W.
Code
+2047
•
•
0
–1
•
•
–2048
A
IN
(V)
+1.024
•
•
0
–0.00049
•
•
–1.024
Digital Output
0111 1111 1111
•
•
0000 0000 0000
1111 1111 1111
•
•
1000 0000 0000
EXPLANATION OF TEST LEVELS
Test Level
I.
II.
100% production tested.
100% production tested at 25°C and sample tested at
specific temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
ORDERING GUIDE
Model
AD10200BZ
5962-9961002HXA
5962-9961001HXA
AD10200/PCB
Temperature Range
–40°C to +85°C (Case)
–40°C to +85°C (Case)
–55°C to +125°C (Case)
Package Description
68-Lead Ceramic Leaded Chip Carrier
68-Lead Ceramic Leaded Chip Carrier
68-Lead Ceramic Leaded Chip Carrier
Evaluation Board with AD10200BZ
Package Option
Z-68B
Z-68B
Z-68B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10200 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD10200
PIN CONFIGURATION
DNC
VREF_A_OUT
SHIELD
AGNDA
AGNDB
AGNDA
AGNDA
AV
CC
AGNDB
DNC
A
IN
A2
NC
A
IN
B2
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
PIN 1
IDENTIFIER
60
59
58
57
56
55
54
AGNDA
10
AGNDA
11
DNC
12
AGNDA
13
AV
CC 14
DNC
15
AGNDA
16
ENCODEA
17
ENCODEA
18
AGNDA
19
DV
CC 20
(MSB) D11A
21
D10A
22
D9A
23
D8A
24
D7A
25
DGNDA
26
NC
AGNDB
DNC
DNC
AGNDB
AGNDB
DNC
DNC
REF_B_OUT
AGNDB
AD10200
TOP VIEW
(Not to Scale)
ENCODEB
ENCODEB
52
AGNDB
51
DV
CC
53
50
49
D0B (LSB)
D1B
48
D2B
47
D3B
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D4B
D5B
DGNDB
DGNDA
D6A
D5A
D4A
D3A
D2A
D1A
AGNDA
AGNDB
(MSB) D11B
D10B
D9B
D8B
D7B
D6B
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2, 5, 9–11, 13, 16, 19, 35
3
6, 62
7
4, 8, 12, 15, 57, 58, 64, 67
14, 66
17
18
20
21–25, 28–34
26, 27
36, 52, 55, 59–61, 65, 68
37–42, 45–50
43, 44
51
53
54
56
63
Mnemonic
SHIELD
AGNDA
VREF_A_OUT
NC
A
IN
A2
DNC
AV
CC
ENCODEA
ENCODEA
DV
CC
D11A–D7A,
D6A–D0A
DGNDA
AGNDB
D11B–D6B,
D5B–D0B
DGNDB
DV
CC
ENCODEB
ENCODEB
VREF_B_OUT
A
IN
B2
Function
Internal Ground Shield between Channels
A Channel Analog Ground. A and B grounds should be connected as close to
the device as possible.
A Channel Internal Voltage Reference
No Connection
Analog Input for A Side ADC
Do Not Connect
Analog Positive Supply Voltage (Nominally 5.0 V)
Complement of Encode
Data conversion initiated on the rising edge of ENCODE input.
Digital Positive Supply Voltage (Nominally 3.3 V)
Digital Outputs for ADC A. D0 (LSB)
A Channel Digital Ground
B Channel Analog Ground. A and B grounds should be connected as close to
the device as possible.
Digital Outputs for ADC B. D0 (LSB)
B Channel Digital Ground
Digital Positive Supply Voltage (Nominally 3.3 V)
Data conversion initiated on rising edge of ENCODE input.
Complement of Encode
B Channel Internal Voltage Reference
Analog Input for B Side ADC
REV. A
(LSB) D0A
–5–
DGNDB
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