Preliminary Technical Data
FEATURES
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply LVDS Comparators
ADCMP604/ACMP605
FUNCTIONAL BLOCK DIAGRAM
V
CCI
V
CCO
(ADCMP605 ONLY)
10 mV sensitivity rail to rail at V
CC
= 2.5 V
Input common-mode voltage from −0.2 V to V
CC
+ 0.2 V
Low glitch LVDS-compatible output stage
1.5 ns propagation delay
35 mW at 2.5 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection >60 dB
−40C° to +125C° operation
V
P
NONINVERTING
INPUT
Q OUTPUT
ADCMP604/
ADCMP605
V
N
INVERTING
INPUT
LVDS
Q OUTPUT
LE/HYS INPUT
S
DN
INPUT
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
(ADCMP605
ONLY)
Figure 1.
GENERAL DESCRIPTION
The ADCMP604 and ADCMP605 are very fast comparators
fabricated on Analog Devices’ proprietary XFCB2 process.
These comparators are exceptionally versatile and easy to use.
Features include an input range from V
EE
− 0.5 V to V
CC
+ 0.5 V,
low noise, LVDS-compatible output drivers, and TTL/CMOS
latch inputs with adjustable hysteresis and/or shutdown inputs.
The devices offer 1.5 ns propagation delays with 1 ps RMS
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps. A flexible power supply scheme allows
the devices to operate with a single +2.5 V positive supply and a
−0.5 V to +3.0 V input signal range up to a +5.5 V positive
supply with a −0.5 V to +6V input signal range.
+
Split input/output supplies, with no sequencing restrictions on
the ADCMP605, support a wide input signal range with greatly
reduced power consumption.
The LVDS-compatible output stage is designed to drive any
standard LVDS input. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded.
High speed latch and programmable hysteresis features are also
provided in a unique single-pin control option.
The ADCMP604 is available in a 6-lead SC70 package. The
ADCMP605 is available in a 12-lead LSCFP package.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
05916-001
APPLICATIONS
ADCMP604/ACMP605
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Preliminary Technical Data
Application Information...................................................................9
Power/Ground Layout and Bypassing........................................9
LVDS-Compatible Output Stage .................................................9
Using/Disabling the Latch Feature..............................................9
Optimizing Performance..............................................................9
Comparator Propagation Delay Dispersion ........................... 10
Comparator Hysteresis .............................................................. 10
Crossover Bias Point .................................................................. 11
Minimum Input Slew Rate Requirement ................................ 11
Typical Application Circuits ......................................................... 12
Timing Information ....................................................................... 13
REVISION HISTORY
2/06—Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 16
Preliminary Technical Data
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
CCI
= V
CCO
= 3.0 V, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
DC INPUT CHARACTERISTICS
Voltage Range
Common-Mode Range
Differential Voltage
Offset Voltage
Bias Current
Offset Current
Capacitance
Resistance, Differential Mode
Resistance, Common Mode
Active Gain
Common-Mode Rejection
Symbol
V
P
, V
N
Conditions
V
CC
= 2.5 V to 5.5 V
V
CC
= 2.5 V to 5.5 V
V
CC
= 2.5 V to 5.5 V
Min
−0.5
−0.2
−5.0
−5.0
−2.0
0.1 V to V
CC
−0.5 V to V
CC
+ 0.5 V
A
V
CMRR
V
CCI
= 2.5 V, V
CCO
= 2.5 V,
V
CM
= −0.2 V to 2.7 V
V
CCI
= 5.5 V, V
CCO
= 5.5 V,
V
CM
= −0.2 V to 5.7 V
R
HYS
= ∞
ADCMP604/ACMP605
Typ
Max
V
CC
+ 0.5 V
V
CC
+ 0.2 V
V
CC
+5.0
+5.0
+2.0
Unit
V
V
V
mV
μA
μA
pF
kΩ
kΩ
dB
dB
dB
mV
V
OS
I
P
, I
N
C
P
, C
N
±2
TBD
100
100
62
50
60
0.1
Hysteresis
LATCH ENABLE PIN CHARACTERISTICS
ADCMP604 only
V
IH
V
IL
L
IH
I
OL
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage
Minimum Resistor Value
Latch Setup Time
Latch Hold Time
Latch to Output Delay
Latch Minimum Pulse Width
SHUTDOWN PIN CHARACTERISTICS
ADCMP605
V
IH
V
IL
I
IH
I
OL
Sleep Time
Wake-Up Time
DC OUTPUT CHARACTERISTICS
Differential Output Voltage Level
ΔV
OD
Common-Mode Voltage
P-P Common-Mode Output
Hysteresis is shut off
Latch mode guaranteed
V
IH
= V
CCO
+ 0.2 V
V
IL
= 0.4 V
Current sink 0 μA
Hysteresis = 16 mV
V
OD
= 100 mV
V
OD
= 100 mV
V
OD
= 100 mV
V
OD
= 100 mV
2.0
−0.2
0.4
V
CC
0.8
0.2
−0.2
1.35
V
V
mA
mA
V
kΩ
ns
ns
ns
ns
1.145
150
1.25
2
5
1.5
2
t
S
t
H
t
PLOH,
t
PLOL
t
PL
t
SD
t
H
V
OD
ΔV
OD
V
OC
V
OC(pp)
Comparator is operating
Shutdown guaranteed
V
IH
= V
CC
V
IL
= 0 V
I
CC
< TBD
V
OD
= 10 mV, output valid
V
CCO
= 2.5 V to 5.5 V
R
LOAD
= 100 Ω
R
LOAD
= 100 Ω
R
LOAD
= 100 Ω
R
LOAD
= 100 Ω
2.0
−0.2
0.4
V
CCO
0.6
0.3
−0.3
50
80
245
1.125
350
445
50
1.375
50
V
V
mA
mA
ns
ns
mV
mV
V
mV
Rev. PrA | Page 3 of 16
ADCMP604/ACMP605
Parameter
AC PERFORMANCE
Propagation Delay
Symbol
t
PD
Conditions
V
CC
= 2.5 V to 5.5 V, V
OD
= 5 mV
V
CCO
= 2.5 V/5.5 V,
V
OD
= 200 mV
V
OD
= 5 mV
10 mV < V
OD
< 2.5 V
5 mV < V
OD
< 2.5 V
.05 V/ns to 2.5 V/ns
2 ns to 20 ns
1 V/ns, V
CM
= 2.5 V
V
CM
= 0.2 V to V
CC
+ 0.2 V
>50% output swing
V
OD
= 200 mV, 5 V/ns
PRBS
31
− 1 NRZ, 0.25 GPS
V
OD
= 200 mV, 5 V/ns
PRBS
31
− 1 NRZ, 0.525 GPS
Δt
PD
/ΔPW < 35 ps
10% to 90%
10% to 90%
@50%
2.5
2.5
−3
−5.5
Min
Preliminary Technical Data
Typ
2
1.5
50
300
500
75
1
200
TBD
TBD
TBD
2
1
1
25
5.5
5.5
+3
+5.5
17
0.8
16
42
100
−50
Max
Unit
ns
ns
ps
ps
ps
ps
ps
ps
Gbps
ns
ps
ns
ns
ns
ps
V
V
V
V
mA
mA
mA
mW
mW
dB
Propagation Delay Skew—Rising to
Falling Transition
Overdrive Dispersion
Slew Rate Dispersion
Pulse Width Dispersion
10% − 90% Duty Cycle Dispersion
Common-Mode Dispersion
Toggle Rate
Deterministic Jitter
TTL/CMOS Outputs
RMS Random Jitter
Minimum Pulse Width
Rise Time
Fall Time
Output Skew
POWER SUPPLY
Input Supply Voltage Range
Output Supply Voltage Range
Positive Supply Differential (ADCMP605)
Positive Supply Differential (ADCMP605)
Positive Supply Current
Input Section Supply Current
(ADCMP605)
Output Section Supply Current
(ADCMP605)
Power Dissipation
(ADCMP605)
Power Supply Rejection
DJ
RJ
PW
MIN
t
R
t
F
T
SKEW
V
CCI
V
CCO
V
CCI
− V
CCO
V
CCI
− V
CCO
I
VCC
I
VCCI
I
VCCO
P
D
P
D
PSRR
Operating
Nonoperating
V
CC
= 2.5 V to 5.5 V
V
CCI
= 5.5 V to 2.5 V
V
CCO
= 5.5 V to 2.5 V
V
CC
= 2.5 V
V
CCI
= 2.5 V to 5 V
Rev. PrA | Page 4 of 16
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltages
Input Supply Voltage (V
CCI
to GND)
Output Supply Voltage
(V
CCO
to GND)
Positive Supply Differential
(V
CCI
− V
CCO
)
Input Voltages
Input Voltage
Differential Input Voltage
Maximum Input/Output Current
Shutdown Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Output Current
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
Rating
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−6.0 V to +6.0 V
ADCMP604/ACMP605
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
−0.5 V to V
CCI
+ 0.5 V
±(V
CCI
+ 0.5 V)
±50mA
−0.5 V to Vcco + 0.5 V
±50
mA
−0.5 V to V
CCO
+ 0.5 V
±50
mA
±50
mA
−40°C to +125°C
150°C
−65°C to +150°C
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
ADCMP604 SC70 6-lead
ADCMP605 LSCFP 12-lead
1
θ
JA 1
TBD
62
Unit
°C/W
°C/W
Measurement in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 5 of 16
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