HY57V643220CLT-5 datasheet, PDF

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HY57V643220CLT-5: Description4 Banks x 512K x 32Bit Synchronous DRAM; Categorystorage storage; File Size179KB，12 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V643220CLT-5 Overview

4 Banks x 512K x 32Bit Synchronous DRAM

HY57V643220CLT-5 Parametric

Parameter Name	Attribute value
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2, TSSOP86,.46,20
Contacts	86
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	4.5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G86
JESD-609 code	e6
length	22.22 mm
memory density	67108864 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	86
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSSOP86,.46,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.002 A
Maximum slew rate	0.28 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN BISMUTH
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
width	10.16 mm

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HY57V643220C

4 Banks x 512K x 32Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V643220C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications

which require wide data I/O and high bandwidth. HY57V643220C is organized as 4banks of 524,288x32.

HY57V643220C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-

puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

JEDEC standard 3.3V power supply

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 86pin TSOP-II with 0.5mm of

pin pitch

All inputs and outputs referenced to positive edge of

system clock

Data mask function by DQM0,1,2 and 3

Internal four banks operation

•

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

•

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

•

ORDERING INFORMATION

Part No.

HY57V643220C(L)T-47

HY57V643220C(L)T-5

HY57V643220C(L)T-55

HY57V643220C(L)T-6

HY57V643220C(L)T-7

HY57V643220C(L)T-8

HY57V643220C(L)T-P

HY57V643220C(L)T-S

Clock Frequency

212MHz

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

Power

Organization

Interface

Package

Normal/

Low Power

4Banks x

512Kbits x32

LVTTL

400mil 86pin

TSOP II

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.8/Aug. 02

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