Edition 2004-05-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
©
Infineon Technologies AG 5/7/04.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide
(www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the human body, or to support and/or maintain and
sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.
.
HYB18T1G400/800/160AF
DATASHEET Rev. 1.02 (05.04)
Features
•
High Performance:
-5
Speed Sorts
DDR2
-400
-3.7
DDR2
-533
-3S
DDR2
-667
-3
DDR2
-667
1Gb DDR2 SDRAM
Units
tck
MHz
Mb/s/pin
Bin
(CL-tRCD-TRP)
max. Clock Frequency
3-3-3 4-4-4 5-5-5 4-4-4
200
400
3
15
15
40
55
266
533
4
15
15
45
60
5
15
15
45
60
333
667
4
12
12
45
57
Data Rate
CAS Latency (CL)
tRCD
tRP
tRAS
tRC
tck
ns
ns
ns
ns
• 1.8V ± 0.1V Power Supply
1.8 V ± 0.1V (SSTL_18) compatible) I/O
• DRAM organisations with 4, 8 and 16 data in/outputs
• Double Data Rate architecture: two data transfers per
clock cycle, eight internal banks for concurrent operation
• CAS Latency: 3, 4 and 5
• Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with
read data and center-aligned with write data
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe opera-
tion
• Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better
command and data bus efficiency
• Off-Chip-Driver impedance adjustment (OCD) and On-Die-
Termination (ODT) for better signal quality.
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power-
Down modes
• Average Refresh Period 7.8µs at a T
CASE
lower than
85
o
C, 3.9µs between 85
o
C and 95
o
C
• Strong and Weak Strength Data-Output Driver
• 1k page size for x 4 & x 8,
2k page size for x16
•
Lead-free Packages:
68 pin FBGA for x4 & x8 components
92 pin FBGA for x16 components
1.0 Description
The 1Gb Double-Data-Rate-2 (DDR2) DRAMs are high-speed
CMOS Double Data Rate 2 Synchronous DRAM devices con-
taining 1,073,741,824 bits and is internally configured as a
octal-bank DRAM. The 1Gb chip is organized as either 32Mbit
x 4 I/O x 8 banks, 16Mbit x 8 I/O x 8 banks or 8Mbit x 16 I/O x 8
banks device. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 667 Mb/sec/pin for gen-
eral applications.
The chip is designed to comply with all key DDR2 DRAM key
features: (1) posted CAS with additive latency, (2) write latency
= read latency -1, (3) normal and weak strength data-output
driver, (4) Off-Chip Driver (OCD) impedance adjustment and
(5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are latched
at the cross point of differential clocks (CK rising and CK fall-
ing). All I/Os are synchronized with a single ended DQS or dif-
ferential (DQS, DQS) pair in a source synchronous fashion. A
17 bit address bus for x 4 and x 8 organised components and a
16 bit address bus for x16 components is used to convey row,
column and bank address information in a RAS / CAS multi-
plexing style.
The DDR2 devices operate with a 1.8V +/-0.1V power supply
and are available in FBGA packages.
An Auto-Refresh and Self-Refresh mode is provided along with
various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
Page 3
Rainer.Weidlich@Infineon.com
Rev. 1.02 May 2004
INFINEON Technologies
京公网安备 11010802033920号
EEWORLD
