The UT54ACS630 is a RadHard 16-bit parallel error detection
and correction circuit. It uses a modified Hamming code to gen-
erate a 6-bit checkword from each 16-bit data word. The check-
word is stored with the data word during a memory write cycle;
during a memory read cycle a 22-bit word is taken from memory
and checked for errors. Single bit errors in the data words are
flagged and corrected. Single bit errors in the checkword are
flagged, but not corrected. The position of the incorrect bit is
pinpointed, in both cases, by the 6-bit error syndrome code
which is output during the error correction cycle.
PIN DESCRIPTION
Pin Names
S0, S1
DBn
CBn
SEF
DEF
Description
Mode Control Inputs
Bidirectional Data Bus
Bidirectional Checkbit Bus
Single Error Flag Output
Double Error Flag Output
28-Lead Flatpack
Top View
DEF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
SEF
S1
S0
CB0
CB1
CB2
CB3
CB4
CB5
DB15
DB14
DB13
DB12
1
FUNCTION TABLES
CONTROL FUNCTIONS
Memory
Cycle
WRITE
READ
READ
READ
Control
S1
Low
Low
High
High
S0
Low
High
High
Low
EDAC
Function
Generates Checkword
Read Data and Check-
word
Latch and Flag Error
Correct Data Word and
Generate Syndrome Bits
Data I/O
Input Data
Input Data
Latch Data
Output Correction
Data
Checkword
Output Checkword
Input Checkword
Latch Checkword
Output Syndrome
Bits
Error Flags
SEF
DEF
Low
Low
Enabled
Enabled
Low
Low
Enabled
Enabled
CHECKWORD GENERATION
Check word bit
CB0
CB1
CB2
CB3
CB4
CB5
0
X
X
X
1
X
X
X
2
X
X
X
3
X
X
4
X
X
X
X
5
X
X
X
6
X
X
X
16-bit data word
7
8
X
X
X
X
X
X
9
X
X
X
X
X
X
X
10
X
11
X
X
X
X
X
X
X
X
12
13
X
14
X
X
X
X
15
ERROR SYNDROME CODES
Syndrome error
code
DB
CB0
CB1
CB2
CB3
CB4
CB5
0
L
L
H
L
H
H
1
L
H
L
L
H
H
2
H
L
L
L
H
H
3
L
L
H
H
L
H
4
L
H
L
H
L
H
5
H
L
L
H
L
H
6
H
L
H
L
L
H
7
H
H
L
L
L
H
8
L
L
H
H
H
L
9
L
H
L
H
H
L
10
L
H
H
L
H
L
11
H
L
H
L
H
L
12
H
H
L
L
H
L
13
L
H
H
H
L
L
14
H
L
H
H
L
L
15
H
H
L
H
L
L
0
L
H
H
H
H
H
1
H
L
H
H
H
H
2
H
H
L
H
H
H
Error locations
CB
3
H
H
H
L
H
H
4
H
H
H
H
L
H
5
H
H
H
H
H
L
No
Error
H
H
H
H
H
H
ERROR FUNCTIONS
Total number of errors
16-bit data
0
1
0
1
2
0
6-bit check word
0
0
1
1
0
2
Error Flags
SEF
L
H
H
H
H
H
DEF
L
L
L
H
H
H
Not applicable
Correction
Correction
Interrupt
Interrupt
Interrupt
Data Correction
2
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEL Immune
SEU Onset LET
Neutron Fluence
2
LIMIT
1.0E5
>108
>108
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
DD
V
I/O
T
STG
T
J
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin during operation
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 6.0
-0.3 to V
DD
+0.3
-65 to +150
+175
20
+10
UNITS
V
V
C
C
C/W
mA
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
t
INRISE
t
INFALL
PARAMETER
Supply voltage
Input voltage any pin
Temperature Range
Max input rise or fall time
(V
IN
transitions between V
IL
(max) and V
IH
(min))
LIMIT
4.5 to 5.5
0 to V
DD
-55 to +125
20
UNITS
V
V
o
C
ns
3
DC ELECTRICAL CHARACTERISTICS
1
( V
DD
= 5.0V +10%; V
SS
= 0V, -55C < T
C
< +125C)
SYMBOL
V
IL
V
IH
I
IN
PARAMETER
Low level input voltage
2
High level input voltage
2
Input leakage current
V
DD
from 4.5V to 5.5V
V
IN
= V
DD
or V
SS
I
OS
Short-circuit output current
3,4
V
O
= V
DD
or V
SS
V
DD
from 4.5V to 5.5V
I
OZ
Three-state output leakage current
V
IN
= V
DD
or V
SS,
V
DD
from
4.5V to 5.5V
I
OL
= 16mA
I
OL
= 100A
V
IN
= V
IH min
or V
IL max
V
DD
from 4.5V to 5.5V
V
OH1
High-level output voltage (except DEF and
SEF)
5
I
OL
= -16mA
I
OL
= -100A
V
IN
= V
IH min
or V
IL max
V
DD
from 4.5V to 5.5V
V
OL2
Low-level output voltage (DEF and SEF
only)
3,4
I
OL
= 8mA
I
OL
= 100A
V
IN
= V
IH min
or V
IL max
V
DD
from 4.5V to 5.5V
V
OH2
High-level output voltage (DEF and SEF
only)
5
I
OL
= -8mA
I
OL
= -100A
V
IN
= V
IH min
or V
IL max
V
DD
from 4.5V to 5.5V
I
DDQ
Quiescent supply current
Pre-Rad -55
o
C to +125
o
C
Post-Rad 25
o
C
I
DD (OP)
V
DD
supply current operating
V
IH
= 5.0V
V
IL
= 0.0V
V
DD
= 5.0V
C
L
=20pF
2
mA/
MHz
V
DD
= 5.5V
V
IN
= V
DD
or V
SS
100
A
V
DD
-0.8
V
DD
-0.2
V
0.4
0.2
V
V
DD
-0.8
V
DD
-0.2
V
-10
+10
A
300
300
mA
0.7 V
DD
-5
+5
CONDITION
MIN
MAX
0.3 V
DD
UNIT
V
V
A
V
OL1
Low-level output voltage (except DEF and
SEF)
5
0.4
0.2
V
4
C
IN
Input capacitance
6
f= 1MHz @ 0V
V
DD
from 4.5V to 5.5V
24
pF
C
OUT
Output capacitance
6
f= 1MHz @ 0V
V
DD
from 4.5V to 5.5V
24
pF
V
IC
+
Positive input clamp voltage
For input under test, I
IN
= 18mA
V
DD
= 0.0V
0.4
1.5
V
V
IC
-
Negative input clamp voltage
For input under test, I
IN
= -18mA
V
DD
= open
-1.5
-0.4
V
P
TOTAL
Power dissipation
7, 8, 9
C
L
= 20pf
V
DD
from 4.5V to 5.5V
400
W/
MHz
Notes:
1. All specifications valid for radiation dose <1E5 rad(Si) per MIL-STD-883, method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
3.Not more than one output may be shorted at a time for maximum duration of one second.
4.Supplied as a design limit, but not guaranteed or tested.
5. Per MIL-PRF-38535, for current density
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
6.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
7.This value is guaranteed based on characterization data, but not tested.
8.Power does not include power contribution of any CMOS output sink current.
9.Power dissipation specified per switching output.
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