DS1646/DS1646P
Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
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Integrates NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identically to the
static RAM. These registers are resident in
the eight top RAM locations
Totally nonvolatile with over 10 years of
operation in the absence of power
Access time of 120 ns and 150 ns
BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100
Power-fail write protection allows for ±10%
V
CC
power supply tolerance
DS1646 only (DIP Module)
−
Standard JEDEC byte-wide 128k x 8
RAM pinout
DS1646P only (PowerCap Module Board)
−
Surface mountable package for direct
connection to PowerCap containing
battery and crystal
−
Replaceable battery (PowerCap)
−
Power-fail output
−
Pin-for-pin compatible with other
densities of DS164XP Timekeeping
RAM
PIN ASSIGNMENT
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-PIN ENCAPSULATED PACKAGE
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC
A15
A16
PFO
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 X1 GND V
BAT
16
17
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
ORDERING INFORMATION
DS1646-XXX
32-pin DIP module
-120
120 ns access
-150
150 ns access
34-pin PowerCap Module
Board
-120
120 ns access
-150
150 ns access
Power Cap
(Required; must be ordered
separately)
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34-PIN POWERCAP MODULE BOARD
(USES DS9034PCX POWERCAP)
*DS1646P-XXX
*DS9034PCX
080299
PIN DESCRIPTION
A0-A16
CE
OE
WE
V
CC
GND
- Address Input
- Chip Enable
- Output Enable
- Write Enable
- +5 Volts
- Ground
DQ0-DQ7
NC
PFO
X1, X2
V
BAT
- Data Input/Output
- No Connection
- Power-fail Output
(DS1646P only)
- Crystal Connection
- Battery Connection
DESCRIPTION
The DS1646 is a 128k x 8 nonvolatile static RAM with a full-function real time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any
JEDEC standard 128k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real
time clock information resides in the eight uppermost RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access
of incorrect data that can occur during clock update cycles. The double-buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1644
also contains its own power-fail circuitry, which deselects the device when the V
CC
supply is in an out-of-
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low V
CC
as errant access and update cycles are avoided.
PACKAGES
The DS1644 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1646P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS - READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1646 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1646 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.
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BLOCK DIAGRAM DS1646
Figure 1
TRUTH TABLE DS1646
Table 1
V
CC
CE
OE
WE
5 VOLTS
±
10%
<4.5 VOLTS >V
BAT
<V
BAT
V
IH
X
V
IL
V
IL
V
IL
X
X
X
X
X
V
IL
V
IH
X
X
X
X
V
IL
V
IH
V
IH
X
X
MODE
DESELECT
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
DQ
HIGH-Z
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
POWER
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
DATA RETENTION
MODE
SETTING THE CLOCK
The 8th bit of the control register is the write bit. Setting the write bit to a 1, like the read bit halts updates
to the DS1646 registers. The user can then load them with the correct day, date and time data in 24-hour
BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and
allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The
OSC
bit is the MSB for the second’s registers. Setting it
to a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the second’s register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e.,
CE
low,
OE
low, and address for seconds register remain valid and stable).
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CLOCK ACCURACY (DIP MODULE)
The DS1646 is guaranteed to keep time accuracy to within
±1
minute per month at 25°C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1646P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within
±1.53
minutes per month (35 PPM) at 25°C.
DS1646 REGISTER MAP - BANK1
Table 2
ADDRESS
1FFF
1FFE
1FFD
1FFC
1FFB
1FFA
1FF9
OSC
1FF8
W
OSC
= STOP BIT
W
= WRITE BIT
B
7
-
X
X
X
X
X
B
6
-
X
X
FT
X
-
-
R
B
5
-
X
-
X
-
-
-
X
DATA
B
4
B
3
-
-
-
-
-
-
X
X
-
-
-
-
-
-
X
X
R = READ BIT
X = UNUSED
B
2
-
-
-
-
-
-
-
X
B
1
-
-
-
-
-
-
-
X
FUNCTION
B
0
-
YEAR
00-99
-
MONTH
01-12
-
DATE
01-31
-
DAY
01-07
-
HOUR
00-23
-
MINUTES
00-59
-
SECONDS
00-59
X
CONTROL
A
FT = FREQUENCY TEST
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1646 is in the read mode whenever
WE
(write enable) is high;
CE
(chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NVSRAM. Valid
data will be available at the DQ pins within t
AA
after the last address input is stable, providing that the
CE
and
OE
access times and states are satisfied. If
CE
or
OE
access times are not met, valid data will be
available at the latter of chip-enable access (t
CEA
) or at output enable access time (t
OEA
). The state of the
data input/output pins (DQ) is controlled by
CE
and
OE
. If the outputs are activated before t
AA
, the data
lines are driven to an intermediate state until t
AA
. If the address inputs are changed while
CE
and
OE
remain valid, output data will remain valid for output data hold time (t
OH
) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1646 is in the write mode whenever
WE
and
CE
are in their active state. The start of a write is
referenced to the latter occurring high to low transition of
WE
and
CE
. The addresses must be held valid
throughout the cycle.
CE
or
WE
must return inactive for a minimum of t
W R
prior to the initiation of
another read or write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a typical application, the
OE
signal will be high during a write cycle. However,
OE
can be
active provided that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on
WE
will then disable the outputs t
WEZ
after
WE
goes active.
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DATA RETENTION MODE
When V
CC
is within nominal limits (V
CC
> 4.5 volts) the DS1646 can be accessed as described above with
read or write cycles. However, when V
CC
is below the power-fail point V
PF
(point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the
CE
signal. At this time the power-fail output signal (
PFO
) will be
driven active low and will remain active until V
CC
returns to nominal levels. When V
CC
falls below the
level of the internal battery supply, power input is switched from the V
CC
pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until V
CC
is returned to nominal
level.
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