343MPLF datasheet, PDF - EEWORLD Datasheet

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343MPLF: DescriptionSOIC-8, Tube; CategoryThe embedded processor and controller Microcontrollers and processors; File Size253KB，10 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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SOIC-8, Tube

343MPLF Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	SOIC-8
Contacts	8
Manufacturer packaging code	DCG8
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G8
JESD-609 code	e3
length	4.9 mm
Humidity sensitivity level	1
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	200 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Master clock/crystal nominal frequency	50 MHz
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage	3.45 V
Minimum supply voltage	3.15 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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DATASHEET

FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER

ICS343

Description

The ICS343 is a low cost, triple-output, field programmable

clock synthesizer. The ICS343 can generate three output

frequencies from 250 kHz to 200 MHz, using up to three

independently configurable PLLs. The outputs may employ

Spread Spectrum techniques to reduce system

electro-magnetic interference (EMI).

Using IDT’s VersaClock™ software to configure the PLL

and output, the ICS343 contains a One-Time

Programmable (OTP) ROM to allow field programmability.

Using Phase-Locked Loop (PLL) techniques, the device

runs from a standard fundamental mode, inexpensive

crystal, or clock. It can replace multiple crystals and

oscillators, saving board space and cost.

The device also has a power down feature that tri-states the

clock outputs and turns off the PLLs when the PDTS pin is

taken low.

The ICS343 is also available in factory-programmed

custom versions for high-volume applications.

Features

•

8-pin SOIC package (Pb-free)

•

Highly accurate frequency generation

•

M/N Multiplier PLL: M = 1...2048, N = 1...1024

•

Output clock frequencies up to 200 MHz

•

Spread spectrum capability for lower system EMI

•

Center or Down Spread up to 4% total

•

Selectable 32 kHz or 120 kHz modulation

•

Input crystal frequency from 5 to 27 MHz

•

Input clock frequency from 2 to 50 MHz

•

Operating voltage of 3.3 V, using advanced, low power

•

CMOS process

For one output clock, use the ICS341. For two output

clocks, see the ICS342. For more than three outputs, see

the ICS345 or ICS348.

Block Diagram

VDD

OTP ROM

with PLL

Divider

Values

Crystal or

clock input

X1/ICLK

Crystal

Oscillator

External capacitors are

required with a crystal input.

CLK1

PLL Clock Synthesis,

Spred Spectrum and

Control Circuitry

CLK2

CLK3

GND

PDTS (both outputs and PLL)

IDT®/ ICS™

FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 1

ICS343

REV M 090613

343MPLF Related Products

	343MPLF	343MPLFT
Description	SOIC-8, Tube	SOIC-8, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Parts packaging code	SOIC	SOIC
package instruction	SOIC-8	SOP, SOP8,.25
Contacts	8	8
Manufacturer packaging code	DCG8	DCG8
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
JESD-30 code	R-PDSO-G8	R-PDSO-G8
JESD-609 code	e3	e3
length	4.9 mm	4.9 mm
Humidity sensitivity level	1	1
Number of terminals	8	8
Maximum operating temperature	70 °C	70 °C
Maximum output clock frequency	200 MHz	200 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP
Encapsulate equivalent code	SOP8,.25	SOP8,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Master clock/crystal nominal frequency	50 MHz	50 MHz
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	1.75 mm
Maximum supply voltage	3.45 V	3.45 V
Minimum supply voltage	3.15 V	3.15 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
width	3.9 mm	3.9 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER
Base Number Matches	1	1

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