HYB/E 25L128160AC
128-MBit Mobile-RAM
128-MBit Synchronous Low-Power DRAM in Chipsize Packages
Datasheet (Rev. 2003-02)
High Performance:
• Automatic and Controlled Precharge
Command
-8
125
8
6
9.5
6
Units
MHz
ns
ns
ns
ns
• Programmable Burst Length: 1, 2, 4, 8 and
full page
• Programmable Power Reduction Feature by
partial array activation during Self-Refresh
• Data Mask for byte control
• Auto Refresh (CBR)
• 4096 Refresh Cycles / 64ms
• Self Refresh with programmble refresh period
• Power Down and Clock Suspend Mode
• Random Column Address every CLK
(1-N Rule)
• 54-FBGA , with 9 x 6 ball array with 3
depopulated rows, 9 x 8 mm
• Operating Temperature Range
Commerical ( 0
0
to 70
0
C)
Extended ( -25
o
C to +85
o
C)
-7.5
f
CK,MAX
t
CK3,MIN
t
AC3,MAX
t
CK2,MIN
t
AC2,MAX
133
7.5
5.4
9.5
6
• 8Mbit x 16 organisation
• VDD = 2.5V, VDDQ = 1.8V / 2.5V
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 1, 2, 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Deep Power Down Mode
The HYB/E 25L128160AC Mobile-RAMs are a new generation of low power, four bank
Synchronous DRAM’s organized as 4 banks
×
2Mbit x16 with additional features for mobile
applications. These synchronous Mobile-RAMs achieve high speed data transfer rates by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated using the Infineon advanced process technology.
The device adds new features to the industry standards set for synchronous DRAM products.
Parts of the memory array can be selected for Self-Refresh and the refresh period during Self-
Refresh is programmable in 4 steps which drastically reduces the self refresh current, depending on
the case temperature of the components in the system application. In addition a “Deep Power Down
Mode” is available. Operating the four memory banks in an interleave fashion allows random access
operation to occur at higher rate. A sequential and gapless data rate is possible depending on burst
length, CAS latency and speed grade of the device. The device operates from a 2.5V power supply
for the core and 1.8V for the bus interface.
The Mobile-RAM is housed in a FBGA “chip-size” package. The Mobile-RAM is available in the
commercial (0
0
to 70
0
C) and Extended ( -25
o
C to +85
o
C) temperature range.
INFINEON Technologies
1
2003-02
HYB/E 25L128160AC
128-MBit Mobile-RAM
Ordering Information
Type
HYB 25L128160AC-7.5
HYB 25L128160AC-8
HYE 25L128160AC-7.5
HYE 25L128160AC-8
Function Code Package
PC133-333-522 BGA-BOC
PC100-222-620 BGA-BOC
PC133-333-522 BGA-BOC
PC100-222-620 BGA-BOC
Description
133 MHz 4B
×
2M x16 LP-SDRAM
100 MHz 4B
×
2M x16 LP-SDRAM
133 MHz 4B
×
2M x16 LP-SDRAM
100 MHz 4B
×
2M x16 LP-SDRAM
Commercial temperature range:
Extended temperature range:
Pin Definitions and Functions
CLK
CKE
CS
RAS
CAS
WE
A0 - A11,
A0 - A8
BA0, BA1
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Row Addresses
Column Addresses
Bank Select
DQ
LDQM, UDQM
Data Input/Output
Data Mask
Power (+ 2.5V)
Ground
Power for DQ’s (+1.8 V)
Ground for DQ’s
Not connected
9
DD
9
SS
9
DDQ
9
SSQ
N.C.
INFINEON Technologies
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2003-02
HYB/E 25L128160AC
128-MBit Mobile-RAM
Pin Configuration for x16 devices:
1
2
3
A
B
C
D
E
F
G
H
J
7
8
9
VDD
DQ1
DQ3
DQ5
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8
NC
VSS
CKE
A9
A6
A4
VDDQ DQ0
VSSQ DQ2
VDDQ DQ4
VSSQ DQ6
VDD LDQM DQ7
CAS
BA0
A0
A3
RAS
BA1
A1
A2
WE
CS
A10
VDD
UDQM CLK
NC
A8
VSS
A11
A7
A5
< Top-view >
INFINEON Technologies
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HYB/E 25L128160AC
128-MBit Mobile-RAM
Functional Block Diagrams
Column Addresses
A0 - A8, AP,
BA0, BA1
Row Addresses
A0 - A11,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Memory
Array
Memory
Array
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Bank 0
4096 x 512
x 16 Bit
Bank 1
4096 x 512
x 16 Bit
Bank 2
4096 x 512
x 16 Bit
Bank 3
4096 x 512
x 16 Bit
Input Buffer
Output Buffer
Control Logic &
Timing Generator
DQ0 - DQ15
Block Diagram: 8Mb x16 SDRAM (12 / 9 / 2 addressing)
INFINEON Technologies
4
CLK
CKE
CS
RAS
CAS
WE
DQMU
DQML
SPB04124
2003-02
HYB/E 25L128160AC
128-MBit Mobile-RAM
Signal Pin Description
Pin
CLK
CKE
Type
Input
Input
Signal Polarity Function
Pulse
Level
Positive The system clock input. All of the SDRAM inputs are
Edge
sampled on the rising edge of the clock.
Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiates either the Power
Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
During a Bank Activate command cycle, A0 - A11 define
the row address (RA0 - RA11) when sampled at the rising
clock edge.
During a Read or Write command cycle, A0-A8 define the
column address (CA0 - CA8) when sampled at the rising
clock edge.
In addition to the column address, A10 (= AP) is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
RAS
CAS
WE
A0 - A11
Input
Pulse
Active
Low
–
Input
Level
BA0, BA1 Input
DQx
Level
–
–
Bank Select Inputs. Selects which bank is to be active.
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
Input Level
Output
INFINEON Technologies
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2003-02
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