8M x 8-Bit Dynamic RAM
(4k & 8k Refresh, EDO-version)
HYB 3164805BJ/BT(L) -40/-50/-60
HYB 3165805BJ/BT(L) -40/-50/-60
Premininary Information
•
•
•
•
8 388 608 words by 4-bit organization
0 to 70 °C operating temperature
Hyper Page Mode - EDO - operation
Performance:
-40
t
RAC
t
CAC
t
AA
t
RC
t
HPC
RAS access time
CAS access time
Access time from address
Read/write cycle time
Hyper page mode (EDO)
cycle time
40
10
20
69
16
-50
50
13
25
84
20
-60
60
15
30
104
25
ns
ns
ns
ns
ns
•
•
Single + 3.3 V (± 0.3V) power supply
Low power dissipation:
max. 306 active mW ( HYB 3164805BJ/BT(L)-40)
max. 252 active mW ( HYB 3164805BJ/BT(L)-50)
max. 216 active mW ( HYB 3164805BJ/BT(L)-60)
max. 486 active mW ( HYB 3165805BJ/BT(L)-40)
max. 396 active mW ( HYB 3165805BJ/BT(L)-50)
max. 324 active mW ( HYB 3165805BJ/BT(L)-60)
7.2 mW standby (LVTTL)
3.6 mW standby (LVMOS)
720
µA
standby for L-version
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh
•
Self refresh (L-version only)
8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164805BJ/BT)
4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165805BJ/BT)
•
128 msec refresh period for L-versions
•
Plastic Package: P-SOJ-32-1
400 mil
HYB 3164(5)400BJ
P-TSOPII-32-1 400 mil
HYB 3164(5)400BT(L)
•
•
Semiconductor Group
1
12.97
HYB3164(5)805BJ/BT(L)-40/-50/-60
8M x 8-DRAM
This HYB3164(5)805B is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is
fabricated in SIEMENS’most advanced 0,25
µm-CMOS
silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. The
HYB3164(5)805B operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL
or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)400B to be packaged in a
400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit
densities and are compatible with commonly used automatic testing and insertion equipment.The
HYB3164(5)805BTL parts have a very low power „ leep mode“supported by Self Refresh.
s
Ordering Information
Type
8k-refresh versions:
HYB 3164805BJ-40
HYB 3164805BJ-50
HYB 3164805BJ-60
HYB 3164805BT-40
HYB 3164805BT-50
HYB 3164805BT-60
HYB 3164805BTL-50
HYB 3164805BTL-60
4k-refresh versions:
HYB 3165805BJ-40
HYB 3165805BJ-50
HYB 3165805BJ-60
HYB 3165805BT-40
HYB 3165805BT-50
HYB 3165805BT-60
HYB 3165805BTL-50
HYB 3165805BTL-60
P-SOJ-32-1
P-SOJ-32-1
P-SOJ-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
400 mil DRAM (access time 40 ns)
400 mil DRAM (access time 50 ns)
400 mil DRAM (access time 60 ns)
400 mil DRAM (access time 40 ns)
400 mil DRAM (access time 50 ns)
400 mil DRAM (access time 60 ns)
400 mil DRAM (access time 50 ns)
400 mil DRAM (access time 60 ns)
P-SOJ-32-1
P-SOJ-32-1
P-SOJ-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
400 mil DRAM (access time 40 ns)
400 mil DRAM (access time 50 ns)
400 mil DRAM (access time 60 ns)
400 mil DRAM (access time 40 ns)
400 mil DRAM (access time 50 ns)
400 mil DRAM (access time 60 ns)
400 mil DRAM (access time 50 ns)
400 mil DRAM (access time 60 ns)
Ordering
Code
Package
Descriptions
Semiconductor Group
2
HYB3164(5)805BJ/BT(L)-40/-50/-60
8M x 8-DRAM
P-SOJ-32-1 (400 mil)
P-TSOPII-32-1 (400 mil)
VCC
I/O1
I/O2
I/O3
I/O4
N.C.
VCC
WE
RAS
.
A0
A1
A2
A3
A4
A5
VCC
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
I/O8
I/O7
I/O6
I/O5
VSS
CAS
OE
A12 / N.C. *
A11
A10
A9
A8
A7
A6
VSS
* Pin 24 is A12 for HYB 3164805BJ/BT(L) and N.C. for HYB 3165805BJ/BT(L)
Pin Configuration
Pin Names
A0-A12
A0-A11
RAS
OE
I/O1-I/O8
CAS
WE
Vcc
Vss
Address Inputs for 8k-refresh version HYB 3164805BJ/BT(L)
Address Inputs for 4k-refresh version HYB 3165805BJ/BT(L)
Row Address Strobe
Output Enable
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply ( + 3.3V)
Ground
Semiconductor Group
3
HYB3164(5)805BJ/BT(L)-40/-50/-60
8M x 8-DRAM
TRUTH TABLE
FUNCTION
Standby
Read
Early-Write
Delayed-Write
Read-Modify-Write
Hyper Page Mode Read 1st Cycle
2nd Cycle
Hyper Page Mode Write 1st Cycle
2nd Cycle
Hyper Page Mode RMW 1st Cycle
2st Cycle
RAS only refresh
CAS-before-RAS refresh
Test Mode Entry
Hidden Refresh
READ
WRITE
Self Refresh
(L-version only)
RAS
H
L
L
L
L
L
L
L
L
L
L
L
H-L
H-L
L-H-L
L-H-L
H-L
CAS
H-X
L
L
L
L
H-L
H-L
H-L
H-L
H-L
H-L
H
L
L
L
L
L
WE
X
H
L
H-L
H-L
H
H
L
L
H-L
H-L
X
H
L
H
L
H
OE
X
L
X
H
L-H
L
L
X
X
L-H
L-H
X
X
X
L
X
X
ROW
ADDR
X
ROW
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
X
X
ROW
ROW
X
COL
ADDR
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
n/a
n/a
COL
COL
X
I/O1-
I/O4
High Impedance
Data Out
Data In
Data In
Data Out, Data In
Data Out
Data Out
Data In
Data In
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
High Impedance
Data Out
Data In
High Impedance
Semiconductor Group
4
HYB3164(5)805BJ/BT(L)-40/-50/-60
8M x 8-DRAM
I/O1
I
/O2
I/O8
WE
CAS
.
&
Data in
Buffer
No. 2 Clock
Generator
8
Data out
Buffer
8
OE
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Column
Address
Buffer(10)
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
8
Refresh
Counter (13)
13
Row
13
1024
x8
Address
Buffers(13)
13
Decoder
8192
8192 x 1024 x 8
Row
Memory Array
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3164805BJ/BT(L)
Semiconductor Group
5
京公网安备 11010802033920号
EEWORLD
