HYB39S16160AT-10 datasheet, PDF

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HYB39S16160AT-10: Description16 MBit Synchronous DRAM; Categorystorage storage; File Size149KB，22 Pages; ManufacturerSIEMENS; Websitehttp://www.infineon.com/

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HYB39S16160AT-10 Overview

16 MBit Synchronous DRAM

HYB39S16160AT-10 Parametric

Parameter Name	Attribute value
Maker	SIEMENS
Parts packaging code	TSSOP
package instruction	,
Contacts	50
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	10 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G50
memory density	16777216 bi
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	50
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX16
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal location	DUAL

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16 MBit Synchronous DRAM

(second generation)

Advanced Information

• High Performance:

CAS latency = 3

-8

125

-10

100

Units

MHz

HYB 39S16400/800/160AT-8/-10

• Multiple Burst Read with Single Write

Operation

• Automatic and Controlled Precharge

Command

• Data Mask for Read/Write control (× 4,

• Dual Data Mask for byte control (× 16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• 4096 refresh cycles/64 ms

• Random Column Address every CLK

(1-N Rule)

• Single 3.3 V

0.3 V Power Supply

• LVTTL Interface versions

• Plastic Packages:

P-TSOPII-44-1 400 mil width (× 4,

P-TSOPII-50-1 400 mil width (× 16)

CK3

AC3

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• 0 to 70

°C

operating temperature

• Dual Banks controlled by A11 (Bank Select)

• Programmable CAS Latency: 1, 2, 3

• Programmable Wrap Sequence: Sequential

or Interleave

• Programmable Burst Length:

1, 2, 4, 8 and full page for Sequential type

1, 2, 4, 8 for Interleave type

The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM’s based on the die revisions “B”

and “C” and organized as 2 banks

2 MBit

4, 2 banks

1 MBit

8 and 2 banks

512 kBit

respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by

employing a chip architecture that prefetches multiple bits and then synchronizes the output data to

a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DRAM process technology.

The device is designed to comply with all JEDEC standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the two memory banks in an interleaved fashion allows random access operation to occur

at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to

125 MHz is possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single

3.3 V

0.3 V power supply and are available in TSOPII packages.

Semiconductor Group

1998-10-01

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