256 MBit Synchronous DRAM
HYB 39S256400/800/160T
Preliminary Information
• High Performance:
-8
-8B
100
10
6
12
7
-10
100
10
7
15
8
Units
MHz
ns
ns
ns
ns
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write control (× 4,
×
8)
• Data Mask for byte control (× 16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 8192 refresh cycles/64 ms 7,8
µ
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V
±
0.3 V Power Supply
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-54 400mil width (× 4,
×
8,
×
16)
• -8 part for PC100 2-2-2 operation
-8B part for PC100 3-2-3 operation
-10 part for PC66 2-2-2 operation
f
CK
t
CK3
t
AC3
t
CK2
t
AC2
•
•
•
•
125
8
6
10
6
Fully Synchronous to Positive Clock Edge
0 to 70
°C
operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3, 4
• Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length:
1, 2, 4, 8
The HYB 39S256400/800/160T are four bank Synchronous DRAM’s organized as
4 banks
×
16 MBit
×
4, 4 banks
×
8 MBit
×
8 and 4 banks
×
4 MBit
×
16 respectively. These syn-
chronous devices achieve high speed data transfer rates for CAS latencies by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated with SIEMENS’ advanced 256 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
±
0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
1
1998-10-01
HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Ordering Information
Type
LVTTL-Version
HYB 39S256400T-8
on request
P-TSOP-54-2 400 mil 125 MHz 4B
×
16 M
×
4 SDRAM
PC100-222-620
P-TSOP-54-2 400 mil 100 MHz 4B
×
16 M
×
4 SDRAM
PC100-323-620
P-TSOP-54-2 400 mil 66 MHz 4B
×
16 M
×
4 SDRAM
PC66-222-820
P-TSOP-54-2 400 mil 125 MHz 4B
×
8 M
×
8 SDRAM
PC100-222-620
P-TSOP-54-2 400 mil 100 MHz 4B
×
8 M
×
8 SDRAM
PC100-323-620
P-TSOP-54-2 400 mil 66 MHz 4B
×
8 M
×
8 SDRAM
PC66-222-820
P-TSOP-54-2 400 mil 125 MHz 4B
×
4 M
×
16 SDRAM
PC100-222-620
P-TSOP-54-2 400 mil 100 MHz 4B
×
4 M
×
16 SDRAM
PC100-323-620
P-TSOP-54-2 400 mil 66 MHz 4B
×
4 M
×
16 SDRAM
PC66-222-820
Ordering
Code
Package
Description
HYB 39S256400T-8B on request
HYB 39S256400T-10 on request
HYB 39S256800T-8
on request
HYB 39S256800T-8B on request
HYB 39S256800T-10 on request
HYB 39S256800T-8
on request
HYB 39S256800T-8B on request
HYB 39S256800T-10 on request
Pin Description and Pinouts
CLK
CKE
CS
RAS
CAS
WE
A0 - A12
BA0, BA1
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
DQ
Data Input/Output
Power (+ 3.3 V)
Ground
Power for DQ’s (+ 3.3 V)
Ground for DQ’s
Not Connected
DQM, LDQM, UDQM Data Mask
V
DD
V
SS
V
DDQ
V
SSQ
NC
Semiconductor Group
2
1998-10-01
HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Column Addresses
A0 - A9, A11, AP
BA0, BA1
Column
Address Counter
Column
Address Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh
Counter
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Sense Amplifier & I(O) Bus
Sense Amplifier & I(O) Bus
Sense Amplifier & I(O) Bus
Bank 0
Bank 1
Bank 2
Sense Amplifier & I(O) Bus
Column Decoder
Column Decoder
Column Decoder
Column Decoder
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank 3
8196 x
2048 x
4 Bit
8196 x
2048 x
4 Bit
8196 x
2048 x
4 Bit
8196 x
2048 x
4 Bit
Input Buffer
Output Buffer
DQ0 - DQ3
Control Logic & Timing Generator
CLK CKE CS RAS CAS WE DQM
V
REF
*)
*) on SSTL versions only
SPB03781
Block Diagram for 64 M
×
4 SDRAM (13/11/2 addressing)
Semiconductor Group
4
1998-10-01
HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Column Addresses
A0 - A9, AP,
BA0, BA1
Column
Address Counter
Column
Address Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh
Counter
Row
Decoder
Sense Amplifier & I(O) Bus
Sense Amplifier & I(O) Bus
Row
Decoder
Sense Amplifier & I(O) Bus
Row
Decoder
Sense Amplifier & I(O) Bus
Row
Decoder
Memory
Array
Bank 3
Column Decoder
Column Decoder
Bank 0
Bank 1
Column Decoder
Bank 2
8192 x
1024 x
8 Bit
8192 x
1024 x
8 Bit
8192 x
1024 x
8 Bit
Column Decoder
Memory
Array
Memory
Array
Memory
Array
8192 x
1024 x
8 Bit
Input Buffer
Output Buffer
DQ0 - DQ7
Control Logic & Timing Generator
CLK CKE CS RAS CAS WE DQM
V
REF
*)
*) on SSTL versions only
SPB03780
Block Diagram for 32 M
×
8 SDRAM (13/10/2 addressing)
Semiconductor Group
5
1998-10-01
Electronics Design Contest
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