HYB511000BJ-70 datasheet, PDF - EEWORLD Datasheet

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HYB511000BJ-70: Description1 M x 1-Bit Dynamic RAM Low Power 1 M ⅴ 1-Bit Dynamic RAM; Categorystorage storage; File Size189KB，22 Pages; ManufacturerSIEMENS; Websitehttp://www.infineon.com/

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HYB511000BJ-70 Overview

1 M x 1-Bit Dynamic RAM Low Power 1 M ⅴ 1-Bit Dynamic RAM

HYB511000BJ-70 Parametric

Parameter Name	Attribute value
Maker	SIEMENS
package instruction	,
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FAST PAGE
Maximum access time	70 ns
Other features	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
JESD-30 code	R-PDSO-J20
memory density	1048576 bi
Memory IC Type	FAST PAGE DRAM
memory width	1
Number of functions	1
Number of ports	1
Number of terminals	20
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX1
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
refresh cycle	512
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal location	DUAL
Base Number Matches	1

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1 M

1-Bit Dynamic RAM

Low Power 1 M

1-Bit Dynamic RAM

HYB 511000BJ-50/-60/-70

HYB 511000BJL-50/-60/-70

Advanced Information

1 048 576 words by 1-bit organization

Fast access and cycle time

50 ns access time

95 ns cycle time (-50 version)

60 ns access time

130 ns cycle time (-60 version)

70 ns access time

130 ns cycle time (-70 version)

•

Fast page mode cycle time

35 ns (-50 version)

40 ns (-60 version)

45 ns (-70 version)

•

Low power dissipation

max. 495 mW active (-50 version)

max. 440 mW active (-60 version)

max. 385 mW active (-70 version)

max. 5.5 mW standby

max. 1.1 mW standby for L-version

•

Single + 5 V (± 10 %) supply with a built-in

generator

Output unlatched at cycle end allows two-

dimensional chip selection

Common I/O capability using “early write”

operation

Read-modify-write, CAS-before-RAS

refresh, RAS-only refresh, hidden-refresh,

fast page mode capability and test mode

capability

All inputs, outputs and clocks

TTL-compatible

512 refresh cycles/8 ms

512 refresh cycles/64 ms

for L-version only

Plastic Packages:

P-SOJ-26/20-1

Ordering Information

Type

HYB 511000BJ-50

HYB 511000BJ-60

HYB 511000BJ-70

HYB 511000BJL-50

HYB 511000BJL-60

HYB 511000BJL-70

Ordering Code

Q67100-Q1056

Q67100-Q518

Q67100-Q519

on request

Q67100-Q526

Q67100-Q527

Package

P-SOJ-26/20-1

Description

DRAM (access time 50 ns)

DRAM (access time 60 ns)

DRAM (access time 70 ns)

DRAM (access time 50 ns)

DRAM (access time 60 ns)

DRAM (access time 70 ns)

Semiconductor Group

01.95

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