4M x 32-Bit Dynamic RAM Module
HYM 324020S/GS-50/-60
Advanced Information
•
•
4 194 304 words by 32-bit organization (alternative 8 388 608 words by 16-bit)
Fast access and cycle time
50 ns access time
90 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
Fast page mode capability
35 ns cycle time (-50 version)
40 ns cycle time (-60 version)
Single + 5 V (± 10 %) supply
Low power dissipation
max. 5280 mW active (HYM 324020S/GS-50)
max. 4840 mW active (HYM 324020S/GS-60)
CMOS – 44 mW standby
TTL
–88 mW standby
CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
8 decoupling capacitors mounted on substrate
All inputs, outputs and clocks fully TTL compatible
72 pin Single in-Line Memory Module with 22.86 mm (900 mil) height
Utilizes eight 4Mx4-DRAMs in 300mil wide SOJ packages
2048 refresh cycles / 32 ms
Optimized for use in byte-write non-parity applications
Tin-Lead contact pads (S - version)
Gold contact pads (GS - version)
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Semiconductor Group
1
12.95
HYM 324020S/GS-50/-60
4M x 32-Bit
The HYM 324020S/GS-50/-60 is a 16 MByte DRAM module organized as 4 194 304 words by
32-bit in a 72-pin single-in-line package comprising eight HYB 5117400BJ 4M x 4 DRAMs in 300
mil wide SOJ-packages mounted together with eight 0.2
µF
ceramic decoupling capacitors on a PC
board.
The HYM 324020S/GS-50/-60 can also be used as a 8 388 608 words by 16-bits dynamic RAM
module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, …, DQ15 and
DQ31, respectively.
Each HYB 5117400BJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 324020S/GS-50/-60 dictates the use of early write cycles.
Ordering Information
Type
HYM 324020S-50
HYM 324020S-60
HYM 324020GS-50
HYM 324020GS-60
Ordering Code
on request
Q67100-Q979
on request
Q67100-Q2005
Package
L-SIM-72-12
L-SIM-72-12
L-SIM-72-12
L-SIM-72-12
Description
DRAM Module
(access time 50 ns)
DRAM Module
(access time 60 ns)
DRAM Module
(access time 50 ns)
DRAM Module
(access time 60 ns)
Semiconductor Group
2
HYM 324020S/GS-50/-60
4M x 32-Bit
Pin Configuration
Pin Names
VSS
DQ16
DQ17
DQ18
DQ19
N.C.
A1
A3
A5
A10
DQ20
DQ21
DQ22
DQ23
N.C.
A8
N.C.
N.C.
N.C.
VSS
CAS2
CAS1
N.C.
WE
DQ8
DQ9
DQ10
DQ11
DQ12
VCC
DQ13
DQ14
DQ15
PD0
PD2
N.C.
1 DQ0 2
3 DQ1 4
5 DQ2 6
7 DQ3 8
9 VCC 10
11 A0
12
13 A2
14
15 A4 16
17 A6 18
19 DQ4 20
21 DQ5 22
23 DQ6 24
25 DQ7 26
27 A7
28
29 VCC 30
31 A9
32
33 RAS2 34
35 N.C. 36
37 N.C. 38
39 CAS0 40
41 CAS3 42
43 RAS0 44
45 N.C. 46
47 N.C. 48
49 DQ24 50
51 DQ25 52
53 DQ26 54
55 DQ27 56
57 DQ28 58
59 DQ29 60
61 DQ30 62
63 DQ31 64
65 N.C. 66
67 PD1 68
69 PD3 70
71 VSS 72
A0-A10
DQ0-DQ31
CAS0 - CAS3
RAS0, RAS2
WE
Address Inputs for
HYM 324020S/GS
Data Input/Output
Column Address Strobe
Row Address Strobe
Read/Write Input
Power (+ 5 V)
Ground
Presence Detect Pin
No Connection
V
CC
V
SS
PD
N.C.
Presence Detect Pins
-50
PD0
PD1
PD2
PD3
-60
V
SS
N.C.
V
SS
N.C.
N.C.
N.C.
V
SS
V
SS
Semiconductor Group
3
HYM 324020S/GS-50/-60
4M x 32-Bit
RAS0
CAS0
DQ0-DQ3
CAS RAS
I/O1-I/O4
OE
D0
CAS RAS
I/O1-I/O4
OE
D1
DQ4-DQ7
CAS1
DQ8-DQ11
CAS RAS
I/O1-I/O4
OE
D2
CAS RAS
I/O1-I/O4
OE
D3
DQ12-DQ15
RAS2
CAS2
CAS RAS
I/O1-I/O4
OE
D4
CAS RAS
I/O1-I/O4
OE
D5
DQ16-DQ19
DQ20-DQ23
CAS3
CAS RAS
I/O1-I/O4
OE
D6
CAS RAS
I/O1-I/O4
D7
OE
D0 - D7
D0 - D7
C0 - C7
VSS
DQ24-DQ27
DQ28-DQ31
A0 - A10
WE
VCC
Block Diagram
Semiconductor Group
4
HYM 324020S/GS-50/-60
4M x 32-Bit
Absolute Maximum Ratings
Operation temperature range ......................................................................................... 0 to + 70 °C
Storage temperature range......................................................................................... – 55 to 125 °C
Input/output voltage ............................................................................–0.5V to min (Vcc+0.5, 7.0) V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation................................................................................................................... 6.72 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 5 V
±
10 %;
t
T
= 5 ns
Parameter
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current
(0 V
≤
V
IH
≤
Vcc + 0.3V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V
≤
V
OUT
≤
Vcc + 0.3V)
Average
V
CC
supply current:
-50 ns version
-60 ns version
(RAS, CAS, address cycling:
t
RC
=
t
RC
min.)
Symbol
Limit Values
min.
max.
Vcc+0.5
0.8
–
0.4
20
10
2.4
– 0.5
2.4
–
– 20
– 10
Unit Test
Condition
V
V
V
V
µA
µA
1)
1)
1)
1)
1)
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
1)
–
–
960
880
16
mA
mA
mA
2) 3) 4)
2) 3) 4)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
Average
V
CC
supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling, CAS =
V
I,H,
t
RC
=
t
RC
min.)
I
CC2
I
CC3
–
–
–
–
960
880
mA
mA
2) 4)
2) 4)
Average
V
CC
supply current,
I
CC4
during fast page mode:
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling:t
PC
=
t
PC
min.)
–
–
320
280
mA
mA
2) 3) 4)
2) 3) 4)
Semiconductor Group
5
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