FT61024
HIGH SPEED 128K x 8
DUAL CHIP ENABLE
CMOS STATIC RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70/85/100/120 ns (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
—32-Pin 600 mil Ceramic DIP
—32-Pin 400 mil Ceramic DIP
—32-Pin Solder Seal Flatpack
—32-Pin LCC (450 x 550 mil)
—32-Pin Ceramic SOJ
DESCRIPTION
The FT61024 is a 1,048,576-bit high-speed CMOS
static RAM organised as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilised to
reduce power consumption to a low level.The FT61024
is a member of a family ofForce Ram products offer-
ing fast access times.
The FT61024 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
.
Reading is accomplished by device selection
CE
1
low
(
and CE
2
high) and output enabling (
OE)
while write
enable (WE) remains HIGH. By presenting the ad-
dress under these conditions, the dat a in the ad-
dressed memory location is presented on the dat a
input/output pins. The input/output pins st ay in the
HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P300, C10, C11),
SOJ (J300, J400, CJ1),
SOLDER SEAL
FLATPACK (FS-3) SIMILAR
LCC (L6)
REV 1
1/15
2008
FT61024
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
(2)
Military
Ambient
Temperature
GND
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
8
10
pF
pF
–55°C to +125°C
–40°C to +85°C
Industrial
Commercial
0°C to +70°C
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
(2)
Over recommended operating temperature and supply voltage
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Test Conditions
FT61024
Min
Max
2.2
V
CC
+0.5
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
2.4
–10
–5
–10
–5
___
___
+10
+5
+10
+5
35
30
25
20
FT61024L
Unit
Min
Max
2.2
V
CC
+0.5 V
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
2.4
–5
n/a
–5
n/a
___
___
+5
n/a
+5
n/a
25
n/a
V
V
V
V
V
V
µA
µA
mA
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
Input Clamp Diode Voltage V
CC
= Min., I
IN
= –18 mA
Output Low Voltage
I
OL
= +8 mA, V
CC
= Min.
(TTL Load)
Output High Voltage
I
OH
= –4 mA, V
CC
= Min.
(TTL Load)
V
CC
= Max.
Mil.
Input Leakage Current
V
IN
= GND to V
CC
Ind./Com’l.
Output Leakage Current
Standby Power Supply
Current (TTL Input Levels)
V
CC
= Max.,
CE
= V
IH
,
V
OUT
= GND to V
CC
Mil.
Ind./Com’l.
I
SB
CE
1
≥
V
IH
or
Mil.
CE
2
≤V
IL
,
Ind./Com’l.
V
CC
= Max,
f = Max., Outputs Open
CE
1
≥
V
HC
or
Mil.
CE
2
≤V
LC
,
Ind./Com’l.
V
CC
= Max,
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
I
SB1
Standby Power Supply
Current
(CMOS Input Levels)
___
___
___
___
2
n/a
mA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUMrating conditions for extended
REV 1
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
2/15
2008
FT61024
HIGH SPEED 128K x 8
DUAL CHIP ENABLE
CMOS STATIC RAM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
I
CC
Dynamic Operating Current* Industrial
Military
-15
-20
-25
-35
-45
-55
-70
-85 -100 -120
Unit
mA
mA
mA
190 160 150 145 N/A N/A N/A N/A N/A N/A
N/A 175 165 160 155 N/A N/A N/A N/A N/A
N/A 150 140 135 130 125 115 110 105 100
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE
1
= V
IL
, CE
2
= V
IH
, OE = V
IH
DATA RETENTION CHARACTERISTICS (FT61024L, Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R†
*
T
A
= +25°C
§
†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Condition
Min
2.0
Typ.*
V
CC
=
2.0V
3.0V
50
200
Max
V
CC
=
2.0V
3.0V
400
600
Unit
V
µA
ns
CE
1
≥
V
CC
– 0.2V or
CE
2
≤
0.2V, V
IN
≥
V
CC
– 0.2V
or V
IN
≤
0.2V
t
RC§
ns
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
REV 1
3/15
2008
FT61024
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
Parameter
Read Cycle
Time
Address
Access Time
Chip Enable
Access Time
Output Hold
from Address
Change
Chip Enable to
Output in Low Z
Chip Disable
to Output in
High Z
Output Enable
Low to Data
Valid
Output Enable
Low to Low Z
Output Enable
High to High Z
Chip Enable to
Power Up
Time
Chip Disable
to Power Down
Time
0
0
7
0
3
3
8
-15
-20
-25
-35
-45
-55
-70
-85
-100
-120
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
15
15
15
3
3
9
20
20
20
3
3
11
25
25
25
3
3
15
35
35
35
3
3
20
45
45
45
3
3
25
55
55
55
3
3
30
70
70
70
3
3
35
85
85
85
3
3
40
100
100
100
3
3
50
120
120
120
ns
ns
ns
ns
ns
ns
t
OE
t
OLZ
t
OHZ
t
PU
7
0
9
0
9
0
11
0
11
0
15
0
15
0
20
0
20
0
25
0
25
0
30
0
30
0
35
0
35
0
40
0
40
0
50
ns
ns
50
ns
ns
t
PD
12
20
20
20
25
30
35
40
45
50
ns
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
OE
Notes:
5.
WE
is HIGH for READ cycle.
8. Transition is measured ± 200 mV from steady state voltage prior to
6.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
change, with loading as specified in Figure 1. This parameter is
7. ADDRESS must be valid prior to, or coincident with
CE
1
transition
sampled and not 100% tested.
LOW and CE
2
transition HIGH.
REV 1
4/15
2008
FT61024
HIGH SPEED 128K x 8
DUAL CHIP ENABLE
CMOS STATIC RAM
TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE
1
, CE
2
CONTROLLED)
(5,7,10)
CE
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether
CE
1
or CE
2
causes them.
REV 1
5/15
2008
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