HYS 64/72V32300GU
SDRAM-Modules
3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules
168-pin Unbuffered DIMM Modules
• 168 Pin unbuffered 8 Byte Dual-In-Line
SDRAM Modules for PC main memory
applications using 256Mbit technology.
• PC100-222, PC133-333 and PC133-222
versions
• One bank 32M
×
64 and 32M
×
72
organisation
• Optimized for byte-write non-parity or ECC
applications
• Fully PC board layout compatible to INTEL’s
Rev. 1.0 module specification
• Programmed Latencies:
Product Speed
-7
-7.5
-8
PC133
PC133
PC100
CL
2
3
2
t
RCD
t
RP
• Single + 3.3 V (
±
0.3 V) power supply
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E
2
PROM
• Uses Infineon 256 Mbit SDRAM components
in 32M
×
8 organization and TSOPII-54
packages
• Gold contact pads, card size:
133.35 mm
×
31.75 mm
×
3.00 mm
(JEDEC MO-161-BA)
2
3
2
2
3
2
• SDRAM Performance:
-7 / -7.5
PC133
f
CK
t
AC
-8
PC100
100
6
Unit
MHz
ns
Clock Frequency (max.)
Clock Access Time
133
5.4
Description
The HYS 64V32300GU and HYS 72V32300GU are industry standard 168-pin 8-byte Dual in-line
Memory Modules (DIMMs) which are organized as 32M
×
64 and 32M
×
72 in 1 memory bank high
speed memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and
ECC applications. The DIMMs use -7 speed sorted 32M
×
8 SDRAM devices in TSOP54 packages
to meet the PC133-222 requirement, -7.5 components for PC133-333 and -8 components for the
standard PC100 applications. Decoupling capacitors are mounted on the PC board. The PC board
design is according to INTEL’s module specification. The DIMMs have a serial presence detect,
implemented with a serial E
2
PROM using the 2-pin I
2
C protocol. The first 128 bytes are utilized by
the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-
pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with
1.25“ (31.75 mm) height.
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
Ordering Information
Type
HYS 64V32300GU-7-D
HYS 72V32300GU-7-D
Code
Package
Descriptions
Module
Height
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
PC133-222-520 L-DIM-168-33 PC133 32M
×
64 1 bank
SDRAM module
PC133-222-520 L-DIM-168-33 PC133 32M
×
72 1 bank
ECC-SDRAM module
HYS 64V32300GU-7.5-C2 PC133-333-520 L-DIM-168-33 PC133 32M
×
64 1 bank
HYS 64V32300GU-7.5-D
SDRAM module
HYS 72V32300GU-7.5-C2 PC133-333-520 L-DIM-168-33 PC133 32M
×
72 1 bank
ECC-SDRAM module
HYS 72V32300GU-7.5-D
HYS 64V32300GU-8-C2
HYS 72V32300GU-8-C2
PC100-222-620 L-DIM-168-33 PC100 32M
×
64 1 bank
SDRAM module
PC100-222-620 L-DIM-168-33 PC100 32M
×
72 1 bank
ECC-SDRAM module
Note: All part numbers end with a place code designating the die revision. Consult factory for
current revision. Example: HYS 64V32300GU-8-C2, indicating Rev. C2 dies are used for
SDRAM components.
Pin Definitions and Functions
A0 - A12
BA0, BA1
CB0 - CB7
RAS
CAS
WE
CKE0
Address Inputs
Bank Selects
CLK0 - CLK3
CS0, CS2
Clock Input
Chip Select
Power (+ 3.3 V)
Ground
Clock for Presence Detect
Serial Data Out for
Presence Detect
No Connection
DQMB0 - DQMB7 Data Mask
DQ0 - DQ63 Data Input/Output
Row Address Strobe
Column Address Strobe
Read/Write Input
Clock Enable
Check Bits (x72 organisation only)
V
DD
V
SS
SCL
SDA
N.C./DU
Address Format
Part Number
Rows Columns
10
Bank Select
2
Refresh Period Interval
8k
64 ms
7.8
µ
s
32M
×
64/72 HYS64/72V32300GU 13
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
Pin Configuration
PIN# Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
N.C. (CB0)
N.C. (CB1)
V
SS
N.C.
N.C.
V
DD
WE
DQMB0
DQMB1
CS0
DU
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CLK0
PIN#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
V
SS
DU
CS2
DQMB2
DQMB3
DU
V
DD
N.C.
N.C.
N.C. (CB2)
N.C. (CB3)
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
N.C.
DU
N.C.
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
N.C.
WP
SDA
SCL
V
DD
PIN#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Symbol
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
N.C. (CB4)
N.C. (CB5)
V
SS
N.C.
N.C.
V
DD
CAS
DQMB4
DQMB5
N.C.
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CLK1
A12
PIN#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
V
SS
CKE0
N.C.
DQMB6
DQMB7
N.C.
V
DD
N.C.
N.C.
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
N.C.
DU
N.C.
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
N.C.
SA0
SA1
SA2
V
DD
Note: Pin names in parantheses are for the x72 ECC versions; example: Pin 106 = (CB5)
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
WE
CS0
DQMB0
DQ(7:0)
CS
WE
DQM
DQ0-DQ7
D0
CS
WE
DQM
DQ0-DQ7
D1
CS
WE
DQM
DQ0-DQ7
D8
DQMB4
DQ(39:32)
CS
WE
DQM
DQ0-DQ7
D4
CS
WE
DQM
DQ0-DQ7
D5
DQMB1
DQ(15:8)
DQMB5
DQ(47:40)
CB(7:0)
CS2
DQMB2
DQ(23:16)
CS
WE
DQM
DQ0-DQ7
D2
CS
WE
DQM
DQ0-DQ7
D3
D0-D7, (D8)
DQMB6
DQ(55:48)
CS
WE
DQM
DQ0-DQ7
D6
CS
WE
DQM
DQ0-DQ7
D7
E PROM (256 word x 8 Bit)
SA0
SA1
SA2
SCL
SA0
SA1
SA2
SCL
SDA
WP
47 k
Ω
2
DQMB3
DQ(31:24)
DQMB7
DQ(63:56)
A0-A12, BA0, BA1
V
CC
V
SS
RAS
CAS
CKE0
D0-D7, (D8)
C0-C15, (C16, C17)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
Clock Wiring
16 M x 64
16 M x 72
5 SDRAM
Termination
4 SDRAM + 3.3 pF
Termination
BL013
Note: D8 is only used in the x72 ECC version and
all resistor values are 10 Ohm except
otherwise noted.
CLK0
CLK1
CLK2
CLK3
4 SDRAM + 3.3 pF
Termination
4 SDRAM + 3.3 pF
Termination
Block Diagram: 32M x 64/72 One Bank SDRAM DIMM Modules
INFINEON Technologies
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HYS 64/72V32300GU
SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
min.
Input / Output voltage relative to V
SS
Power supply voltage on V
DD
Storage temperature range
Power dissipation per SDRAM component
Data out current (short circuit)
V
IN,
V
OUT
V
DD
T
STG
P
D
I
OS
– 1.0
– 1.0
-55
–
–
Limit Values
max.
4.6
4.6
+150
1
50
V
V
o
Unit
C
W
mA
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
DD
= 3.3 V
±
0.3 V
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage (
I
OUT
= – 4.0 mA)
Output Low Voltage (
I
OUT
= 4.0 mA)
Input Leakage Current, any input
(0 V <
V
IN
< 3.6 V, all other inputs = 0 V)
Output Leakage Current
(DQ is disabled, 0 V <
V
OUT
<
V
DD
)
Symbol
min.
Limit Values
max.
2.0
– 0.5
2.4
–
– 40
– 40
Unit
V
V
V
V
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
V
DD
+ 0.3
0.8
–
0.4
40
40
µ
A
µ
A
T
A
= 0 to 70
°
C;
V
DD
= 3.3 V
±
0.3 V,
f
= 1 MHz
Parameter
Symbol
Limit Values
max.
32M x 64
Input Capacitance
(
A0 to A11, BA0, BA1, RAS, CAS, WE)
Input Capacitance (CS0 - CS3)
Input Capacitance (CLK0 - CLK3)
Input Capacitance (CKE0)
Input Capacitance (DQMB0 - DQMB7)
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance
max.
32M x 72
72
40
40
72
16
10
8
8
pF
pF
pF
pF
pF
pF
pF
pF
Unit
Capacitance
C
I1
C
I2
C
ICL
C
I3
C
I4
C
SC
C
SD
65
32
38
65
13
10
8
8
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
C
IO
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