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IDT70V07S55GG

Description
Dual-Port SRAM, 32KX8, 55ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, PGA-68
Categorystorage    storage   
File Size163KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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IDT70V07S55GG Overview

Dual-Port SRAM, 32KX8, 55ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, PGA-68

IDT70V07S55GG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codePGA
package instructionPGA,
Contacts68
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time55 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
JESD-30 codeS-CPGA-P68
JESD-609 codee3
length29.464 mm
memory density262144 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Number of functions1
Number of ports2
Number of terminals68
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height5.207 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperature30
width29.464 mm
Base Number Matches1
HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 25/35/55ns (max.)
– Industral: 25ns (max.)
Low-power operation
– IDT70V07S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V07L
Active: 300mW (typ.)
Standby: 660
µ
W (typ.)
Interrupt Flag
IDT70V07S/L
IDT70V07 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 80-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
14L
A
0L
(1,2)
I/O
Control
I/O
0R
-I/O
7R
,
BUSY
R
Address
Decoder
15
(1,2)
MEMORY
ARRAY
15
Address
Decoder
A
14R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
M/S
SEM
R
INT
R(2)
2943 drw 01
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
OCTOBER 2004
1
DSC 2943/6
©2004 Integrated Device Technology, Inc.
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