ICL7134UJMJI datasheet, PDF - EEWORLD Datasheet

®

December 1997

N OT

RE

NDE

MME

CO

R

D FO

NEW

IG

DES

NS

ICL7134

14-Bit Multiplying

Microprocessor-Compatible D/A Converter

Description

The ICL7134 combines a four-quadrant multiplying DAC

using thin film resistor and CMOS circuitry with an on-chip

PROM-controlled correction circuit to achieve true 14-bit

linearity without laser trimming.

Microprocessor bus interfacing is eased using standard

memory WRITE cycle timing and control signal use. Two

input buffer registers are separately loaded with the 8 least

significant bits (LS register) and the 6 most significant bits

(MS register). Their contents are then transferred to the

14-bit DAC register, which controls the current switches. The

DAC register can also be loaded directly from the data

inputs, in which case the MS and LS registers are

transparent.

The ICL7134 is available in two versions. The ICL7134U is

programmed for unipolar operation while the ICL7134B is

programmed for bipolar applications. The V

REF

input to the

most significant bit of the DAC is separated from the

reference input to the remainder of the ladder. For unipolar

use, the two reference inputs are tied together, while for

bipolar operation, the polarity of the MSB reference is

reversed, giving the DAC a true 2’s complement input

transfer function. Two resistors which facilitate the reference

inversion are included on the chip, so only an external

op-amp is needed. The PROM is coded to correct for errors

in these resistors as well as the inversion of the MSB.

Features

• 14-Bit Linearity (0.003% FSR)

• No Gain Adjustment Necessary

• Microprocessor-Compatible with Double Buffered

Inputs

• Bipolar Application Requires No Extra Adjustments or

External Resistors

• Low Linearity and Gain Temperature Coefficients

• Low Power Dissipation

• Full Four-Quadrant Multiplication

• 883B Processed Versions Available

Ordering Information

TEMPERATURE RANGE (

o

C)

NON-LINEARITY AT 25

o

C

BIPOLAR VERSIONS

0.01% (12-bit)

0.006% (13-bit)

0.003% (14-bit)

UNIPLAR VERSIONS

0.01% (12-bit)

0.006% (13-bit)

0.003% (14-bit)

ICL7134UJCJI

ICL7134UKCJI

ICL7134ULCJI

ICL7134UJIJI

ICL7134UKIJI

ICL7134ULIJI

ICL7134UJMJI

ICL7134UKMJI

ICL7134ULMJI

28 Ld CERDIP

ICL7134BJCJI

ICL7134BKCJI

ICL7134BLCJI

ICL7134BJIJI

ICL7134BKIJI

ICL7134BLIJI

ICL7134BJMJI

ICL7134BKMJI

ICL7134BLMJI

28 Ld CERDIP

0 to 70

-25 to 85

-55 to 125

PACKAGE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

|

Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

File Number

3113.1

ICL7134

Pinout

ICL7134

(OUTLINE DWG JI)

TOP VIEW

CS 1

WR

(LSB) D

0

D

1

D

2

D

3

D

4

D

5

D

6

2

3

4

5

6

7

8

9

28 A

0

27 A

1

26 V+

25 I

OUT

24 AGND

S

23 AGND

F

22 DGND

21 R

FB

20 V

RFM

19 R

INV

18 V

RFL

17 PROG

16 D

13

(MSB)

15 D

12

D

7

10

D

8

11

D

9

12

D

10

13

D

11

14

Functional Block Diagram

2

ICL7134

Pin Descriptions

28 LEAD

CERDIP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

NAME

CS

WR

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

10

D

11

D

12

D

13

PROG

V

RFL

R

INV

V

RFM

R

FB

DGND

Chip Select (active low). Enables register write.

WRITE, (active low). Writes in register. Equivalent to CS.

Bit 0

Bit1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Input Data Bits (High = True)

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Most significant

Least Significant

PIN DESCRIPTION

Used for programming only. Tie to +5V for normal operation.

V

REF

for lower bits.

Summing node for reference inverting amplifier.

FV

REF

for MSB only (bipolar)

Feedback resistor for voltage output applications.

Digital Ground Return.

AGND

F

Analog Ground force lines. Use to carry current from internal Analog GND connections. Tied internally to AGND

S

.

AGND

S

Analog Ground sense line. Reference point for external circuitry. Pin should carry minimal current; tied internally to

AGND

F

.

I

OUT

V+

A

1

A

0

Current output pin.

Positive Supply.

Address 1

Address 0

Registers Select Lines

25

26

27

28

3

ICL7134

Absolute Maximum Ratings

(Note 1)

Supply Voltage (V+ to DGND) . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V

V

RFL

, V

RFM

, R

INV

, R

FB

to DGND

. . . . . . . . . . . . . . . . . . . . . . . . ±15V

I

OUT

, AGND

F

, AGND

S

. . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to V+

Current in AGND

S

, AGND

F

. . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA

An, Dn, WR, CS, PROG . . . . . . . . . . . . . . . . . . . . -0.3V to V+ +0.3V

Thermal Information

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65

o

C to 150

o

C

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW

Derate Linearly Above 70

o

C @10mW/

o

C

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300

o

C

Operating Conditions

Temperature Range

ICL7134XXC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0

o

C to 70

o

C

ICL7134XXI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25

o

C to 85

o

C

ICL7134XXM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55

o

C to 125

o

C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. All voltages with respect to DGND.

2. Assumes all leads soldered or welded to printed circuit board.

Electrical Specification

PARAMETER

DC ACCURACY

Resolution

Non-Linearity

V+ = +5V, V

REF

= +10V, T

A

= 25

o

C, AGND = DGND, I

OUT

at Ground Potential,

Unless Otherwise Specified.

TEST CONDITIONS

MIN

TYP

MAX

UNITS

14

(Notes 3 and 4) Figure 2

J

K

L

-

J

K

L

12

13

14

-

±1

-

±2

-

±60

±10

-

±0.012

±0.006

±0.003

±2

-

±0.024

±0.012

±0.006

±8

±10

-

Bits

%FSR

ppm/

o

C

Bits

%FSR

ppm/

o

C

nA

ppm/month

Non-Linearity Temperature

Coefficient

Monotonicity

Operating Temperature Range (Note 5)

(Note 5)

Gain Error

(Notes 3 and 4)

Figure 1

J

K

L

Gain Error Temperature

Coefficient

Output Leakage Current

(I

OUT

Terminal)

Long Term Stability of I

OUT

AC ACCURACY

Power Supply Rejection

(Note 5)

T

A

= 25

o

C

Operating Temperature Range

1000 Hours, 125

o

C, (Note 5)

∆V+

=

±10%,

Figure 2, T

A

= 25

o

C

Operating Temperature Range

-

U

B

-

±10

-

250

500

1

±100

±150

-

ppm/V

µV

P-P

µV

P-P

µs

Feedthrough Error

V

REF

= 20V

P-P

, 2kHz

Sinewave, Figure 3

Output Current Setting Time

Output Noise

To 1/2 LSB, Figure 4

Equivalent to Johnson Noise of 7kΩ Resistor, Typical

4

ICL7134

Electrical Specification

PARAMETER

REFERENCE INPUT

Input Resistance

ANALOG OUTPUT

Output Capacitance

(I

OUT

Terminal)

DIGITAL INPUTS

Low State Threshold

High State Threshold

Input Current

Input Capacitance

POWER SUPPLY

Supply Voltage Range

Supply Current

NOTES:

3. Full-Scale Range (FSR) is 10V for unipolar mode, 20V (±10V) for bipolar mode.

4. Using internal feedback and reference inverting resistors.

5. Guaranteed by design, not production tested.

6. Gain error tested to 0.040% FSR, Specifications are not guaranteed.

7. D0 - D13 connected to 2.4V.

Functional Operation, (Note 6)

Excluding Ladder Network (Note 7)

3.5

-

1.0

6.0

2.5

V

mA

Inputs between DGND to V+

(Note 5)

Operating Temperature Range

-

2.4

-

15

0.8

-

±1

-

V

µA

pF

DAC Register Outputs All LOW

DAC Register Outputs All HIGH

-

160

235

-

pF

V

RFL

= V

RFM

, I

OUT

at Ground

4

7

10

kΩ

V+ = +5V, V

REF

= +10V, T

A

= 25

o

C, AGND = DGND, I

OUT

at Ground Potential,

Unless Otherwise Specified.

(Continued)

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Switching Specifications

PARAMETER

Address-WRITE Set-Up Time

Address-WRITE Hold Time

V+ = 5V, T

A

= 25

o

C, See Timing Diagram

SYMBOL

t

AWs

t

AWh

t

CWs

t

CWh

t

WR

t

DWs

t

DWh

Note 5

TEST CONDITIONS

MIN

150

0

200

0

TYP

-

MAX

-

UNITS

ns

CHIP SELECT-WRITE Set-Up Time

CHIP SELECT-WRITE Hold Time

WRITE Pulse Width Low

Data-WRITE Set-Up Time

Data-WRITE Hold Time

5

ICL7134UJMJI

ICL7134UJMJI Overview

Preview

Recommended Resources