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XCV200E-7FGG256I

Description
Field Programmable Gate Array, 1176 CLBs, 63504 Gates, 400MHz, 5292-Cell, CMOS, PBGA256, FBGA-256
CategoryProgrammable logic devices    Programmable logic   
File Size927KB,99 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Environmental Compliance
Download Datasheet Parametric View All

XCV200E-7FGG256I Overview

Field Programmable Gate Array, 1176 CLBs, 63504 Gates, 400MHz, 5292-Cell, CMOS, PBGA256, FBGA-256

XCV200E-7FGG256I Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerXILINX
Parts packaging codeBGA
package instructionBGA, BGA256,16X16,40
Contacts256
Reach Compliance Codecompliant
ECCN codeEAR99
maximum clock frequency400 MHz
Combined latency of CLB-Max0.42 ns
JESD-30 codeS-PBGA-B256
JESD-609 codee1
length17 mm
Humidity sensitivity level3
Configurable number of logic blocks1176
Equivalent number of gates63504
Number of entries176
Number of logical units5292
Output times176
Number of terminals256
organize1176 CLBS, 63504 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA256,16X16,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)260
power supply1.2/3.6,1.8 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height2 mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Terminal surfaceTin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width17 mm
Base Number Matches1
R
Spartan-II FPGA Family
Data Sheet
Product Specification
DS001 June 13, 2008
This document includes all four modules of the Spartan
®
-II FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS001-1 (v2.8) June 13, 2008
Introduction
Features
General Overview
Product Availability
User I/O Chart
Ordering Information
Module 3:
DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
DC Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
Switching Characteristics
- Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
Module 2:
Functional Description
DS001-2 (v2.8) June 13, 2008
Architectural Description
- Spartan-II Array
- Input/Output Block
- Configurable Logic Block
- Block RAM
- Clock Distribution: Delay-Locked Loop
- Boundary Scan
Development System
Configuration
- Configuration Timing
Design Considerations
Module 4:
Pinout Tables
DS001-4 (v2.8) June 13, 2008
Pin Definitions
Pinout Tables
IMPORTANT NOTE:
This Spartan-II FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001 June 13, 2008
Product Specification
www.xilinx.com
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