3D7408S-5 datasheet, PDF - EEWORLD Datasheet

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3D7408S-5: DescriptionSilicon Delay Line, Programmable, 1-Func, 255-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16; Categorylogic logic; File Size64KB，7 Pages; ManufacturerData Delay Devices; Environmental Compliance

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3D7408S-5 Overview

Silicon Delay Line, Programmable, 1-Func, 255-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16

3D7408S-5 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Data Delay Devices
Parts packaging code	SOIC
package instruction	SOP, SOP16,.4
Contacts	16
Reach Compliance Code	compliant
series	CMOS/TTL
Input frequency maximum value (fmax)	0.31 MHz
JESD-30 code	R-PDSO-G16
length	10.3 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	255
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	40 mA
programmable delay line	YES
Prop。Delay @ Nom-Sup	1292 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	1292 ns
width	7.5 mm
Base Number Matches	1

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3D7408

MONOLITHIC 8-BIT

PROGRAMMABLE DELAY LINE

(SERIES 3D7408)

FEATURES

•

All-silicon, low-power CMOS technology

TTL/CMOS compatible inputs and outputs

Vapor phase, IR and wave solderable

Auto-insertable (DIP pkg.)

Low ground bounce noise

Leading- and trailing-edge accuracy

Increment range:

0.25 through 5.0ns

Delay tolerance:

1% (See Table 1)

Temperature stability:

±3%

typical (0C-70C)

Vdd stability:

±1%

typical (4.75V-5.25V)

Minimum input pulse width:

10% of total

delay

Programmable via 3-wire serial or 8-bit

parallel interface

SO/P0

GND

data

delay

devices,

inc.

PACKAGES

VDD

OUT

SO/P0

GND

VDD

OUT

3D7408 DIP

3D7408G Gull Wing

(300 Mil)

3D7408S

SOIC

(300 Mil)

(For mechanical data, see Case Dimensions document)

FUNCTIONAL DESCRIPTION

The 3D7408 Programmable 8-Bit Silicon Delay Line product

family consists of 8-bit, user-programmable CMOS silicon

integrated circuits. Delay values, programmed either via the

serial or parallel interface, can be varied over 255 equal steps

ranging from 250ps to 5.0ns inclusively. Units have a typical

inherent (zero step) delay of 12ns to 17ns (See Table 1). The

input is reproduced at the output without inversion, shifted in time

as per user selection. The 3D7408 is TTL- and CMOS-

compatible, capable of driving ten 74LS-type loads, and features

both rising- and falling-edge accuracy.

PIN DESCRIPTIONS

OUT

P0-P7

VCC

GND

Signal Input

Signal Output

Mode Select

Address Enable

Parallel Data Input

Serial Clock

Serial Data Input

Serial Data Output

+5 Volts

Ground

The all-CMOS 3D7408 integrated circuit has been designed as a reliable, economic alternative to hybrid

TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving

surface mount 16-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

PART

NUMBER

3D7408-0.25

3D7408-0.5

3D7408-1

3D7408-2

3D7408-3

3D7408-4

3D7408-5

DELAYS AND TOLERANCES

Step 0

Delay (ns)

Step 255

Delay (ns)

75.75

4.0

139.5

4.0

267.0

5.0

522.0

6.0

782.0

8.0

1037

9.0

1292

Delay

Increment (ns)

0.25

0.15

0.50

0.25

1.00

0.50

2.00

1.00

3.00

1.50

4.00

2.00

5.00

2.50

Max Operating

Frequency

6.25 MHz

3.15 MHz

1.56 MHz

0.78 MHz

0.52 MHz

0.39 MHz

0.31 MHz

INPUT RESTRICTIONS

Absolute Max

Oper Freq

90 MHz

45 MHz

22 MHz

11 MHz

7.5 MHz

5.5 MHz

4.4 MHz

Min Operating

P.W.

80.0 ns

160.0 ns

320.0 ns

640.0 ns

960.0 ns

1280.0 ns

1600.0 ns

Absolute Min

Oper P.W.

5.5 ns

11.0 ns

22.0 ns

44.0 ns

66.0 ns

88.0 ns

110.0 ns

NOTES: Any delay increment between 0.25 and 5.0 ns not shown is also available.

All delays referenced to input pin

1996 Data Delay Devices

Doc #96003

12/2/96

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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