ICS307
Serially Programmable Clock Source
Description
The ICS307-01 and ICS307-02 are versatile
serially programmable clock sources which take
up very little board space.
They can generate any frequency from 6 to
200 MHz, and have a second configurable
output. The outputs can be reprogrammed on
the fly, and will lock to a new frequency in 10 ms
or less. Smooth transitions (in which the clock
duty cycle remains roughly 50%) are guaranteed
if the output divider is not changed.
The devices include a PDTS pin which tri-states
the output clocks and powers down the entire
chip.
The ICS307-02 features a default clock output
at start-up and is recommended for all new
designs.
Features
• Packaged as 16 pin narrow SOIC
• Highly accurate frequency generation
• Serially programmable: user determines
the output frequency via a 3 wire interface.
• Eliminates need for custom quartz
• Input crystal frequency of 5 - 27 MHz
• Output clock frequencies up to 200 MHz
• Power Down Tri-State mode
• Very low jitter
• Operating voltages of 3.0 to 5.5 V
• 25 mA drive capability at TTL levels
• Industrial temperature available
Block Diagram
TTL
2
Shift
Register
3
2
R6:R0
7
VDD GND
SCLK
DATA
STROBE
C1:C0
S2:S0
F1:F0
9
V8:V0
Output
Buffer
VCO
Divider
S2:S0
3
VCO
Output
Divider
PDTS
CLK1
Crystal or
clock input
X1/ICLK
Reference
Divider
Phase Comparator,
Charge Pump,
and Loop Filter
Crystal
Oscillator
X2
Function
Select
2
F1:F0
Output
Buffer
TTL
CLK2
C1:C0
MDS 307 D
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Revision 042501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel •www.icst.com
ICS307
Serially Programmable Clock Source
Pin Assignment
ICS307
X1/ICLK
NC
VDD
NC
GND
CLK2
NC
SCLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
NC
NC
PDTS
DATA
CLK1
NC
STROBE
16 pin Narrow
(0.150”) SOIC
Pin Description
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
X1/ICLK
NC
VDD
NC
GND
CLK2
NC
SCLK
STROBE
NC
CLK1
DATA
PDTS
NC
NC
X2
Type
XI
-
P
-
P
O
-
I
I
-
O
I
I
-
-
XO
Description
Crystal connection (REF frequency). Connect to a parallel resonant crystal, or an input clock .
No Connect.
Connect to +3.3V or +5V.
No Connect.
Connect to ground.
Output clock 2, determined by F0-F1. Can be reference, ref/2, CLK1/2 or off.
No Connect.
Serial clock. See timing diagram.
Strobe to load data. See timing diagram.
No Connect.
Output clock 1, determined by R0-R6, V0-V8, S0-S2 and input frequency.
Data Input. Serial input for three words which set the output clock(s).
Powers down entire chip, tri-states CLK1 and CLK2 outputs, when low. Internal pull-up.
No Connect.
No Connect.
Input crystal connection. Connect to a crystal, or leave unconnected for clock input.
Type: XI, XO=crystal connections, I = Input, O = output, P = power supply connection
MDS 307 D
2
Revision 042501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel •www.icst.com
ICS307
Serially Programmable Clock Source
Determining the Output Frequency
On power-up the ICS307-01 on-chip registers can have random values, so almost any frequency may be
output from the part. CLK1 will always have some clock signal present, but CLK2 could possibly be OFF
(low).
The ICS307-02 on-chip registers are initially configured to provide a x1 output clock on both the CLK1
and CLK2 outputs. The output frequency will be the same as the input clock or crystal. This is useful if
the ICS307 will provide the initial system clock at power-up. Since this feature is an advantage in most
systems, the ICS307-02 is recommended for new designs.
With programming, the user has full control in changing the desired output frequency to any value over the
range shown in Table 1 on page 4. The output of the ICS307 can be determined by the following simple
equation:
(VDW+8)
CLK1 frequency = Input frequency • 2 • (RDW+2)(OD)
Where
VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3 are not permitted)
Reference Divider Word (RDW) = 1 to 127 (0 is not permitted)
Output Divider = values on page 4
Also, the following operating ranges should be observed:
(VDW+8)
55 MHz < Input frequency • 2 • (RDW+2)
200 kHz <
Input Frequency
(RDW+2)
< 400 MHz
Commercial temperature range.
Industrial temperature limits are
60 MHz to 360 MHz.
To determine the best combination of VCO, reference, and output dividers, contact ICS application
engineering. You may also fax this page to ICS at 408 295 9818(fax). Be sure to indicate the following:
Your Name ________________ Company Name___________________ Telephone_________________
Respond by e-mail (list your e-mail address) __________________or fax number ___________________
Desired input crystal_______ or clock_______ (in MHz) Desired output frequency_______________
REF Output_______VDD = 3.3V or 5V _______ Duty Cycle: 40-60% _____ or 45-55% required____
MDS 307 D
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Revision 042501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel •www.icst.com
ICS307
Serially Programmable Clock Source
Setting the Device Characteristics
The tables below show the settings which can be configured, in addition to the VCO and Reference dividers.
Table 1. Output Divide and
Maximum Output Frequency
Max. Freq.
CLK1
Maximum
Industrial
S2 S1 S0 Output
Frequency
Version
Divide
5 V or 3.3 V
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
2
8
4
5
7
3
6
40
200
50
100
80
55
135
67
36
180
45
90
72
50
120
60
Table 2. CLK2 Output
F1
0
0
1
1
F0
0
1
0
1
CLK2
REF
REF/2
OFF (Low)
CLK1/2
0 = Connect directy to ground
1 = Connect directly to VDD
Table 3. Output Duty Cycle Configuration
TTL
0
1
Duty cycle measured at
1.4V
VDD/2
Recommended VDD
5V
3.3 V
Table 4. Crystal Load Capacitance
C1
0
0
1
1
C0
0
1
0
1
VDD = 5 V
22.3 - 0.083 f
23.1 - 0.093 f
23.7 - 0.106 f
24.4 - 0.120 f
VDD = 3.3 V
22.1 - 0.094 f
22.9 - 0.108 f
23.5 - 0.120 f
24.2 - 0.135 f
Note: The TTL bit optimizes the duty cycle at
different VDD. When VDD is 5 V, set to 0
for a near-50% duty cycle with TTL levels.
When VDD is 3.3 V, set this bit to a 1, so the
50% duty cycle is achieved at VDD/2.
Note: f is the crystal frequency, between 10 and
27 MHz. Effective load capacitance will be higher
for crystal frequencies lower than 10 MHz. If a
clock input is used, set C1 = 0 and C0 = 0.
MDS 307 D
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Revision 042501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel •www.icst.com
ICS307
Serially Programmable Clock Source
Configuring the ICS307
The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are
written to the DATA pin, in this order:
C1 C0
TTL
F1 F0
MSB
S2
S1
S0
LSB
V8 V7 V6 V5 V4 V3 V2 V1
MSB
LSB
V0 R6 R5 R4 R3 R2 R1 R0
MSB
LSB
C1 is loaded into the port first and R0 last.
R6:R0
V8:V0
S2:S0
F1:F0
TTL
C1:C0
Reference Divider Word (RDW)
VCO Divider Word (VDW)
Output Divider Select (OD)
Function of CLK2 Output
Duty Cycle Setting
Internal Load Capacitance for Crystal
Power up default values for ICS 307-02
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
The input frequency will come from both outputs.
Programming Example
To generate 66.66 MHz from a 14.31818 MHz input, the RDW should be 59, the VDW should be 276,
and the Output Divide is 2. Selecting the minimum internal load capacitance, CMOS duty cycle, and CLK2
to be OFF means that the following three bytes are sent to the ICS307:
00110001
Byte 1
10001010
Byte 2
00111011
Byte 3
As shown in Figure 2, after these 24 bits are clocked into the ICS307, taking STROBE high will send this data
to the internal latch, and the CLK output will lock within 10 ms.
NOTE: If STROBE is in the high state and SCLK is pulsed, DATA is clocked directly to the internal latch
and the output conditions will change accordingly. Although this will not damage the ICS307, it is
recommended that STROBE be kept low while DATA is being clocked into the ICS307 in order to avoid
unintended changes on the output clocks.
MDS 307 D
5
Revision 042501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel •www.icst.com
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