PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
LVCMOS F
ANOUT
B
UFFER
F
EATURES
•
18 LVCMOS outputs, 7Ω typical output impedance
•
Output frequency up to 200MHz
•
150ps output skew
•
Part to part skew: TBD
•
Selectable LVCMOS or differential clock input
•
LVTTL / LVCMOS clock select input
•
Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS83940-02 is a low skew, 1-to-18 Fanout
Buffer and a member of the HiPerClockS™
HiPerClockS™
family of High Performance Clock Solutions from
ICS. The low impedance LVCMOS out-
puts are designed to drive 50Ω series or parallel
terminated transmission lines. The effective fanout can be in-
creased from 18 to 36 by utilizing the ability of the outputs to
drive two series terminated lines. The differential clock
input is designed to accept any differential input levels
including LVPECL.
,&6
The ICS83940-02 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS83940 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
VDDO
GND
Q0
Q1
Q2
Q3
Q4
Q5
CLK_SEL
CLK0
nCLK0
LVCMOS_CLK
GND
Q0
1
32 31 30 29 28 27 26 25
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q17
Q16
Q15
GND
Q14
Q13
Q12
VDDO
24
23
22
Q6
Q7
Q8
VDDO
Q9
Q10
Q11
GND
GND
LVCMOS_CLK
Q1 - Q16
CLK_SEL
CLK
nCLK
ICS83940-02
21
20
19
18
17
Q17
VDDI
VDDO
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83940AY-02
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 6, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
LVCMOS F
ANOUT
B
UFFER
Name
GND
Type
Power
Input
Input
Input
Input
Power
Power
Output
Description
Output power supply ground. Connect to ground.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 12, 17, 25
3
4
5
6
7
8, 16, 21, 29
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
LVCMOS_CLK
CLK_SEL
CLK
nCLK
VDDI
VDDO
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Pulldown Clock input. LVCMOS interface levels.
Clock select input. Select LVCMOS clock input
Pulldown when HIGH. Selects LVPECL clock inputs when
LOW.
Non-inver ting differential clock input. Any differential
Pulldown
inteface levels.
Inver ting differential clock input. Any differential
Pullup
inteface levels.
Input power supply. Connect to 3.3V or 2.5V.
Output power supply. Connect to 3.3V or 2.5V.
Clock outputs. 7
W
typical output impedance.
LVCMOS interface levels
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
CIN
Parameter
Input
Capacitance
CLK0, nCLK0,
LVCMOS_CLK
CLK_SEL
VDDI, VDDO = 3.465V
CPD
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
VDDI = 3.465V,
VDDO = 2.625V
VDDI, VDDO = 2.625V
RPULLUP
RPULLDOWN
ROUT
51
51
7
Test Conditions
Minimum Typical
Maximum
4
4
Units
pF
pF
pF
pF
K
W
pF
K
W
W
83940AY-02
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 6, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
LVCMOS F
ANOUT
B
UFFER
Clock
CLK0, nCLK0
Selected
De-selected
LVCMOS_CLK
De-selected
Selected
T
ABLE
3A. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0
1
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK-SEL
0
0
0
0
0
0
1
LVCMOS_CLK
—
—
—
—
—
—
0
CLK0
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
—
nCLK0
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
—
Outputs
Q0 thru
Q17
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
Non Inver ting
1
1
—
—
HIGH
Single Ended to Single Ended Non Inver ting
NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets
the switch point for the single ended input. For LVCMOS input levels the recommended input bias network is a resistor to
VDDI, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is
VDDI/2.
83940AY-02
www.icst.com/products/hiperclocks.html
3
REV. A AUGUST 6, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
LVCMOS F
ANOUT
B
UFFER
4.6V
-0.5V to VDD+0.5 V
-0.5V to VDD+0.5V
46°C/W (0lfpm)
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, VDD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, Tstg
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
T
ABLE
4A. DC C
HARACTERISTICS
,
VDDI = VDDO = 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
VDDI
VDDO
IDD
Input Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
VDDI = VDDO = 3.465V
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
70
Units
V
V
mA
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
VDDI = VDDO = 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
VIH
VIL
Input High Voltage
Input Low Voltage
REF_CLK
CLK_SEL
REF_CLK
CLK_SEL
REF_CLK,
CLK_SEL
REF_CLK,
CLK_SEL
Test Conditions
VDDI = 3.465V
VDDI = 3.135V
VDDI = 3.135V
VDDI = VIN = 3.465V
VDDI = 3.465V, VIN = 0V
VDDO = 3.135V,
IOH = -36mA
VDDO = 3.135V,
IOL = 36mA
-5
2.4
0.6
Minimum
2
-0.3
-0.3
Typical
Maximum
3.8
1.3
0.8
150
Units
V
V
V
µA
µA
V
V
IIH
IIL
VOH
VOL
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
VDDI = VDDO = 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
IIH
IIL
VPP
Input High Current
Input Low Current
CLK0
nCLK0
CLK0
nCLK0
Test Conditions
VDDI = VIN = 3.465V
VDDI = VIN = 3.465V
VDDI = 3.465V, VIN = 0V
VDDI = 3.465V, VIN = 0V
-5
-150
1.3
VDD - 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Input Common Mode Voltage;
VCMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
83940AY-02
www.icst.com/products/hiperclocks.html
4
REV. A AUGUST 6, 2001
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
LVCMOS F
ANOUT
B
UFFER
Test Conditions
CLK, nCLK
CLK, nCLK
0
<
f
£
200MHz
0
<
f
£
200MHz
Measured on rising edge
@VDDO/2
Measured on rising edge
@VDDO/2
20% to 80% @ 50MHz
20% to 80% @ 50MHz
Minimum Typical
2.3
Maximum
200
4
Units
MHz
ns
ns
ps
ps
ns
ns
55
%
T
ABLE
5A. AC C
HARACTERISTICS
,
VDDI = VDDO = 3.3V±5%, T
A
= 0°
TO
70°
Symbol
fMAX
tpLH
tpHL
tsk(o)
tsk(pp)
tR
tF
Parameter
Maximum Input Frequency
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
150
TBD
odc
Output Duty Cycle
45
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions, and using the same type of inputs.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY-02
www.icst.com/products/hiperclocks.html
5
REV. A AUGUST 6, 2001
京公网安备 11010802033920号
EEWORLD
