Integrated
Circuit
Systems, Inc.
ICS840002-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
F
EATURES
• Two LVCMOS/LVTTL outputs @ 3.3V,
17Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Output frequency range: 56MHz - 175MHz
• VCO range: 560MHz - 700MHz
• Output skew: 12ps (maximum)
• RMS phase jitter at 156.25MHZ (1.875MHz - 20MHz):
0.47ps (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -97.4 dBc/Hz
1kHz .............. -120.2 dBc/Hz
10kHz .............. -127.6 dBc/Hz
100kHz .............. -126.1 dBc/Hz
• Full 3.3V or 3.3V core/2.5V output supply mode
• -30°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS840002-01 is a 2 output LVCMOS/LVTTL
Synthesizer optimized to generate Ethernet
HiPerClockS™
reference clock frequencies and is a member of
the HiPerClocks
TM
family of high performance
clock solutions from ICS. Using a 25MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
156.25MHz, 125MHz, and 62.5MHz. The ICS840002-01 uses
ICS’ 3
rd
generation low phase noise VCO technology and can
achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS840002-01 is
packaged in a small 16-pin TSSOP package.
IC
S
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
F_SEL1 F_SEL0
0
0
1
1
0
1
0
1
M Divider Value
25
25
25
25
Output Frequency
(25MHz Ref.)
N Divider Value
4
5
10
5
156.25
125
62.5
125
B
LOCK
D
IAGRAM
OE
Pullup
F_SEL1:0 Pullup:Pullup
nPLL_SEL Pulldown
nXTAL_SEL
XTAL_IN
Pulldown
25MHz
P
IN
A
SSIGNMENT
2
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
V
DD
Q0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F_SEL1
GND
GND
Q0
Q1
V
DDO
XTAL_IN
XTAL_OUT
OSC
XTAL_OUT
TEST_CLK Pulldown
0
F_SEL1:0
1
Phase
Detector
00
01
10
11
1
VCO
0
N
÷4
÷5
÷10
÷5
ICS840002-01
Q1
M = ÷25 (fixed)
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
MR
840002AG-01
Pulldown
www.icst.com/products/hiperclocks.html
REV. B JANUARY 13, 2006
1
Integrated
Circuit
Systems, Inc.
ICS840002-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
Type
Input
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Description
Frequency select pin. LVCMOS/LVTTL interface levels.
Selects between the cr ystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Single-ended LVCMOS/LVTTL clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing active outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency =
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Cr ystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Output supply pin.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
Name
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
6
7
8
9,
10
11
12, 13
14, 15
16
nPLL_SEL
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
V
DDO
Q1, Q0
GND
F_SEL1
Input
Power
Power
Input
Power
Output
Power
Input
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
3.3V±5%
2.5V±5%
14
16
Test Conditions
Minimum
Typical
4
8
51
51
17
21
21
25
Maximum
Units
pF
pF
kΩ
kΩ
Ω
Ω
840002AG-01
www.icst.com/products/hiperclocks.html
2
REV. B JANUARY 13, 2006
Integrated
Circuit
Systems, Inc.
ICS840002-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
2.375
Typical
3.3
3.3
3.3
2.5
Maximum
3.465
3.465
3.465
2.625
100
12
5
Units
V
V
V
V
mA
mA
mA
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -30°C
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input
High Current
OE, F_SEL0, F_SEL1
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
OE, F_SEL0, F_SEL1
I
IL
Input
Low Current
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DDO
= 3.465V±5%
V
DDO
= 2.5V±5%
V
DDO
= 3.3V or 2.5V±5%
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
DD
+ 0.3
0.8
5
150
-150
-5
2.6
1.8
0.5
Units
V
V
µA
µA
µA
µA
V
V
V
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information, Output Load Test Circuits.
840002AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 13, 2006
3
Integrated
Circuit
Systems, Inc.
ICS840002-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
Typical
25
50
7
1
Maximum
Units
MHz
Ω
pF
mW
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
Fundamental
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -30°C
TO
85°C
Symbol
f
OUT
t
sk(o)
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 3
156.25MHz (1.875MHz - 20MHz)
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
125MHz (1.875MHz - 20MHz)
62.5MHz (1.875MHz - 20MHz)
20% to 80%
200
0.47
0.57
0.51
700
54
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10 or 11
Minimum
14 0
11 2
56
Typical
Maximum
175
140
70
12
Units
MH z
MHz
MHz
ps
ps
ps
ps
ps
%
odc
Output Duty Cycle
46
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -30°C
TO
85°C
Symbol
f
OUT
t
sk(o)
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 3
156.25MHz (1.875MHz - 20MHz)
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
125MHz (1.875MHz - 20MHz)
62.5MHz (1.875MHz - 20MHz)
20% to 80%
200
0.47
0.55
0.49
700
54
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10 or 11
Minimum
140
112
56
Typical
Maximum
175
14 0
68
12
Units
MHz
MHz
MH z
ps
ps
ps
ps
ps
%
odc
Output Duty Cycle
46
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840002AG-01
www.icst.com/products/hiperclocks.html
4
REV. B JANUARY 13, 2006
Integrated
Circuit
Systems, Inc.
ICS840002-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE AT
62.5MH
Z
@3.3V
0
-10
-20
-30
-40
-50
➤
1Gb Ethernet Filter
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.51ps (typical)
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
Raw Phase Noise Data
➤
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
➤
10k
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
1M
10M
100M
100k
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
156.25MH
Z
@3.3V
0
-20
-30
-40
-50
➤
10Gb Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.47ps (typical)
-10
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-170
-180
-190
100
1k
10k
100k
-160
Raw Phase Noise Data
➤
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
1M
10M
100M
REV. B JANUARY 13, 2006
➤
O
FFSET
F
REQUENCY
(H
Z
)
840002AG-01
www.icst.com/products/hiperclocks.html
5
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