LAN91C110 REV. B
PRELIMINARY
FEAST Fast Ethernet Controller
for PCMCIA and Generic 16-Bit Applications
FEATURES
Dual Speed CSMA/CD Engine (10 Mbps and 100
Mbps)
Compliant with IEEE 802.3 100BASE-T
Specification
Supports 100BASE-TX, 100BASE-T4
16 Bit Wide Data Path (into Packet Buffer Memory)
Generic 16-bit System Level Interface Easily
Adaptable to ISA, PCMCIA (16-bit CardBus), and
Various CPU System Interfaces
Support for 16 and 8 Bit CPU Accesses
Asynchronous Bus Interface
128 Kbyte External Memory
Built-in Transparent Arbitration for Slave Sequential
Access Architecture
Early TX, Early RX Functions
Flat MMU Architecture with Symmetric Transmit
and Receive Structures and Queues
IEEE-802.3 MII (Media Independent Interface)
Compliant MAC-PHY Interface Running at Nibble
Rate
MII Management Serial Interface
IEEE-802.3u Full Duplex Capability
144 Pin TQFP Package (1.0 Millimeter Height)
GENERAL DESCRIPTION
The LAN91C110 is designed to facilitate the implementation of second generation Fast Ethernet PC Card adapters and
other non-PCI connectivity products. The LAN91C110 is a digital device that implements the Media Access Control (MAC)
portion of the CSMA/CD protocol at 10 and 100 Mbps, and couples it with a lean and fast data and control path system
architecture to ensure that the CPU to packet RAM data movement does not cause a bottleneck at 100 Mbps.
The LAN91C110 implements a generic 16-bit host interface which is adaptable to a wide range of system buses and
CPUs. This makes the LAN91C110 ideal for 10/100 Fast Ethernet implementations in systems based on system buses
other than PCI.
Total memory size is 128 Kbytes, equivalent to a total chip storage (transmit plus receive) of 64 outstanding packets. The
LAN91C110 is software compatible with the LAN9000 family of products in the default mode and can use existing
LAN9000 drivers (ODI, IPX, and NDIS) with minor modifications in 16 and 32 bit Intel X86 based environments.
Memory management is handled using a unique patented MMU (Memory Management Unit) architecture and an
internal 32-bit wide data path. This I/O mapped architecture can sustain back-to-back frame transmission and
reception for superior data throughput and optimal performance. It also dynamically allocates buffer memory in an
efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from performing these
housekeeping functions. The total memory size is 128 Kbytes (external), equivalent to a total chip storage (transmit
and receive) of 64 outstanding packets.
FEAST provides a flexible slave interface for easy connectivity with industry-standard buses. The host interface is
“ISA-like” and is easily adapted to a wide range of system and CPU buses such as ISA, PCMCIA, etc.
An IEEE-802.3 compliant Media Independent Interface (MII) provided on the network side of the LAN91C110. The MII
interface allows the use of a wide range of MII compliant Physical Layer (PHY) devices to be used with the LAN91C110.
The LAN91C110 also provides an interface to the two-line MII serial management protocol.
SMSC DS – LAN91C110 REV. B
Page 1
Rev. 09/05/02
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
ORDERING INFORMATION
Order Number:
LAN91C110TQFP
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC DS – LAN91C110 REV. B
Page 2
Rev. 09/05/02
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
TABLE OF CONTENTS
FEATURES................................................................................................................................1
GENERAL DESCRIPTION ........................................................................................................1
FUNCTIONAL DESCRIPTION ..................................................................................................9
DATA STRUCTURES AND REGISTERS...............................................................................13
T
YPICAL
F
LOW OF
E
VENTS FOR
T
RANSMIT
(A
UTO
R
ELEASE
= 0) ..................................................36
T
YPICAL
F
LOW OF
E
VENTS FOR
T
RANSMIT
(A
UTO
R
ELEASE
= 1) ..................................................37
T
YPICAL
F
LOW OF
E
VENTS FOR
R
ECEIVE
.....................................................................................38
OPERATIONAL DESCRIPTION .............................................................................................46
MAXIMUM GUARANTEED RATINGS* ...................................................................................46
DC ELECTRICAL CHARACTERISTICS..................................................................................46
TIMING DIAGRAMS ................................................................................................................49
LAN91C110 REV. B REVISIONS ..........................................................................................55
LIST OF TABLES
T
ABLE
1 - DESCRIPTION OF PIN FUNCTIONS........................................................................................................5
T
ABLE
2 - BUFFER TYPES ..........................................................................................................................................7
T
ABLE
3 - I
NTERNAL
I/O S
PACE
M
APPING
.....................................................................................................................16
T
ABLE
4 - P
IN
P
ACKAGE
O
UTLINE
T
ABLE
....................................................................................................................54
LIST OF FIGURES
F
IGURE
1 - PIN CONFIGURATION .............................................................................................................................4
F
IGURE
2 - LAN91C110 BLOCK DIAGRAM ..............................................................................................................8
F
IGURE
3 - LAN91C110 SYSTEM DIAGRAM............................................................................................................8
F
IGURE
4 - LAN91C110 INTERNAL BLOCK DIAGRAM WITH DATAPATH......................................................12
F
IGURE
5 - DATA PACKET FORMAT ......................................................................................................................13
F
IGURE
6 - INTERRUPT STRUCTURE .....................................................................................................................31
F
IGURE
7 - INTERRUPT SERVICE ROUTINE .........................................................................................................39
F
IGURE
8- RX INTR ....................................................................................................................................................40
F
IGURE
9 - TX INTR....................................................................................................................................................41
F
IGURE
10 - TXEMPTY INTR (A
SSUMES AUTO RELEASE OPTION SELECTED
)............................................................42
F
IGURE
11 - DRIVE SEND AND ALLOCATE ROUTINES......................................................................................43
F
IGURE
12 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU ....................................................45
F
IGURE
13 - ASYNCHRONOUS CYCLE -
N
ADS=0.................................................................................................49
F
IGURE
14 - ASYNCHRONOUS CYCLE - USING
N
ADS ........................................................................................49
F
IGURE
15 - ADDRESS LATCHING FOR ALL MODES..........................................................................................50
F
IGURE
16 - SRAM INTERFACE ...............................................................................................................................51
F
IGURE
17 - MII I
NTERFACE
........................................................................................................................................53
F
IGURE
18 - 144 P
IN
TQFP P
ACKAGE
O
UTLINES
.........................................................................................................54
SMSC DS – LAN91C110 REV. B
Page 3
Rev. 09/05/02
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
A10
A11
VDD
A12
A13
A14
A15
GND
nBE0
nBE1
D7
nLDEV
D6
D5
D4
GND
D3
D2
D1
D0
ARDY
GND
INT0
nRD
VDD
nWR
RESET
GND
MCLK
AEN
AUISEL
MDO
MDI
AGND
N/C
AVDD
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
nLNK
XTAL1
XTAL2
VDD
nCSOUT
TX25
RX_ER
RX_DV
GND
RX25
COL100
CRS100
RXD0
RXD1
RXD2
RXD3
GND
TXD0
TXD1
VDD
TXD2
TXD3
TXEN100
nRWE0
RD7
RD6
RD5
RD4
GND
RD3
RD2
RD1
VDD
RD0
RD15
RD14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LAN91C110
144 Pin TQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
A9
A8
A7
A6
A5
A4
A3
A2
A1
GND
D8
D9
VDD
D10
D11
D12
D13
D14
GND
D15
nADS
VDD
RA16
RA14
RA15
RA9
RA10
RA8
RA11
VDD
nROE
RA7
GND
RA13
RA6
RA5
SMSC DS – LAN91C110 REV. B
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
RA12
RA4
RA3
GND
nRWE3
RA2
VDD
RD24
RD25
RD26
RD27
RD28
RD29
GND
nRWE2
RD30
RD31
VDD
RD16
RD17
RD18
RD19
RD20
GND
RD21
RD22
RD23
RD8
nRWE1
VDD
RD9
RD10
RD11
GND
RD12
RD13
FIGURE 1 - PIN CONFIGURATION
Page 4
Rev. 09/05/02
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
TABLE 1 - DESCRIPTION OF PIN FUNCTIONS
144 TQFP
NAME
PIN NO.
115-112, Address
110-100
138
Address
Enable
118, 117
SYMBOL
A[15:1]
AEN
nBE[1:0]
BUFFER
TYPE
I
I
I
DESCRIPTION
Input. Used by LAN91C110 for internal register
selection.
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
Input. Used during LAN91C110 register accesses
to determine the width of the access and the
register(s) being accessed.
Bidirectional. 16-bit data bus used to access the
LAN91C110’s internal registers. Data bus has
weak internal pullups. Supports direct connection
to the system bus without external buffering.
Input. This input is not considered active unless it
is active for at least 100ns to filter narrow glitches.
Open drain output. ARDY may be used when
interfacing asynchronous buses to extend
accesses. Its rising (access completion) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus clock.
Note: Asserted for 100 to 150ns for the
appropriate NO WAIT bit state in the Configuration
register. See the NO WAIT bit description for
complete information.
Output. Local Device. This active low output is
asserted when AEN is low and A4-A15 decode to
the LAN91C110 address programmed into the
high byte of the Base Address Register. nLDEV*
is a combinatorial decode of unlatched address
and AEN signals.
Input. Address strobe. For systems that require
address latching. The rising edge of nADS
indicates the latching moment of A[1:15] and AEN.
All LAN91C110 internal functions of A[1:15] and
AEN are latched.
Output. The interrupt output is enabled by
selecting the appropriate routing bits (INT SEL 1-
0) in the Configuration Register.
Input. Used in asynchronous bus interfaces.
Input. Used in asynchronous bus interfaces.
Bidirectional. Carries the local buffer memory
read and write data. Reads are always 32 bits
wide. Writes are controlled individually at the byte
level.
89, 91-95, Data Bus
97-98, 119,
121-123,
125-128
135
Reset
129
D[15:0]
I/O8
RESET
IS
OD16
Asynchro- ARDY
nous
Ready
120
Local
Device
nLDEV
O16
88
nAddress nADS
Strobe
IS
131
Interrupt
INTR0
O4
132
134
56-57, 60-
65, 46-48,
50-54, 35-
38, 40-42,
45, 25-28,
30-32, 34
nRead
nRD
Strobe
nWrite
nWR
Strobe
RAM Data RD[31:0]
Bus
IS
IS
I/O4 with
pullups
SMSC DS – LAN91C110 REV. B
Page 5
Rev. 09/05/02
京公网安备 11010802033920号
EEWORLD
