PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
•
TEST_CLK can accept the following input levels:
LVCMOS or LVTTL
•
Maximum FOUT frequency: 700MHz
•
Maximum FOUT/2 frequency: 350MHz
•
VCO range: 200MHz to 700MHz
•
Parallel interface for programming counter and
VCO frequency multiplier and dividers
•
Cycle-to-cycle jitter: 25ps (maximum)
•
RMS period jitter: TBD
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8432-11 is a general purpose, dual output
Crystal-to-3.3V Differential LVPECL High Frequency
HiPerClockS™
Synthesizer and a member of the HiPerClock™
S
family of High Performance Clock Solutions from
ICS. The ICS8432-11 has a selectable TEST_CLK
or crystal inputs. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to 3.3V LVPECL
levels. The VCO operates at a frequency range of 200MHz
to 700MHz. The VCO frequency is programmed in steps
equal to the value of the input reference or crystal frequency.
Output frequencies up to 700MHz for FOUT and 350MHz
for FOUT/2 can be programmed using the serial or parallel
interfaces to the configuration logic. The low phase noise
characteristics and the multiple frequency outputs of the
ICS8432-11 makes it an ideal clock source for Fiber Channel
1 and 2, and Infiniband applications.
ICS
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
P
IN
A
SSIGNMENT
XTAL_OUT
VCO_SEL
nP_LOAD
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
M5
M6
M7
M8
N0
N1
nc
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT/2
nFOUT/2
V
CCO
FOUT
nFOUT
V
EE
24
23
22
XTAL_IN
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8432-11
21
20
19
18
17
MR
FOUT
nFOUT
FOUT/2
nFOUT/2
V
EE
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432CY-11
www.icst.com/products/hiperclocks.html
1
REV. E MAY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
nP_LOAD or until a serial event occurs. As a result, the M and
N bits can be hardwired to set the M divider and N output divider
to a specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the paral-
lel input mode. The relationship between the VCO frequency,
the input frequency and the M divider is defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 8
≤
M
≤
28. The frequency out is defined as follows:
fOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output
divider when S_LOAD transitions from LOW-to-HIGH. The
M divide and N output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and
N output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout/2
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes
operation using a 25MHz clock input. Valid PLL loop divider
values for different input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-11 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
ICS8432-11. This input is fed into the phase detector. A 25MHz
clock input provides a 25MHz phase detector reference fre-
quency. The VCO of the PLL operates over a range of 200MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjust-
ing the VCO control voltage. Note, that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent
to each of the LVPECL output buffers. The divider provides
a 50% output duty cycle.
The programmable features of the ICS8432-11 support two
input modes to program the PLL M divider and N output
divider. The two input operational modes are parallel and
serial.
Figure1
shows the timing diagram for each mode. In
parallel mode, the nP_LOAD input is initially LOW. The data
on inputs M0 through M8 and N0 and N1 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the
M divider remains loaded until the next LOW transition on
S
ERIAL
L
OADING
S_CLOCK
S_DATA
S_LOAD
T1
T0
*
NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
nP_LOAD
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
M, N
S_LOAD
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
8432CY-11
The NULL timing slot must be observed.
www.icst.com/products/hiperclocks.html
2
REV. E MAY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Type
Input
Input
Input
Unused
Power
Output
Power
Output
Power
Output
Pullup
M divider inputs. Data latched on LOW-to-HIGH transistion of
Pulldown nP_LOAD input. LVCMOS / LVTTL interface levels.
Pulldown
Determines N output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
No connect.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
Core supply pin.
Half frequency differential output for the synthesizer.
3.3V LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are rset causing the true outputs (FOUTx) to go low and the
inver ted outputs (nFOUTx) to go high. When logic LOW, the
internal dividers and the outputs are enabled. Asser tion of MR
does not affect loaded M, N, and T values.
LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between crystal or test inputs as the PLL reference
source. LVCMOS / LVTTL interface levels. Selects XTAL inputs
when HIGH. Selects TEST_CLK when LOW.
Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator inputs. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
8, 16
9
10
11, 12
13
14, 15
Name
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
V
EE
TEST
V
CC
FOUT/2, nFOUT/2
V
CCO
FOUT, nFOUT
17
MR
Input
Pulldown
18
19
20
21
22
23
24,
25
26
27
S_CLOCK
S_DATA
S_LOAD
V
CCA
XTAL_SEL
TEST_CLK
XTAL_IN,
XTAL_OUT
nP_LOAD
VCO_SEL
Input
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
8432CY-11
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
www.icst.com/products/hiperclocks.html
3
REV. E MAY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Inputs
T
ABLE
3A. P
ARALLEL
MR
H
L
L
nP_LOAD
X
L
↑
AND
S
ERIAL
M
ODES
F
UNCTION
T
ABLE
N
X
Data
Data
S_LOAD
X
X
L
S_CLOCK
X
X
X
S_DATA
X
X
X
Conditions
Reset. M and N counters reset.
Data on M and N inputs passed directly to the
M divider. TEST output forced LOW.
Data is latched into input registers and remains
loaded until next LOW transition or until a serial
event occurs.
Serial input mode. Shift register is loaded with
data on S_DATA on each rising edge of
S_CLOCK.
Contents of the shift register are passed to the
M divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is
clocked.
M
X
Data
Data
L
L
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
↑
↓
L
H
↑
L
L
X
↑
Data
Data
Data
X
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
200
225
250
275
•
•
650
675
M Divide
8
9
10
11
•
•
26
27
256
M8
0
0
0
0
•
•
0
0
128
M7
0
0
0
0
•
•
0
0
64
M6
0
0
0
0
•
•
0
0
32
M5
0
0
0
0
•
•
0
0
16
M4
0
0
0
0
•
•
1
1
8
M3
1
1
1
1
•
•
1
1
4
M2
0
0
0
0
•
•
0
0
2
M1
0
0
1
1
•
•
1
1
1
M0
0
1
0
1
•
•
0
1
0
700
28
0
0
0
0
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency of
25MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
8432CY-11
Output Frequency (MHz)
N Divider Value
N0
0
1
0
1
1
2
4
8
Minimum
200
100
50
25
FOUT
Maximum
700
350
175
87.5
FOUT/2
Minimum
Maximum
125
62.5
31.25
15.625
350
175
87.5
43.75
REV. E MAY 20, 2005
www.icst.com/products/hiperclocks.html
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
110
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
Input
S_DATA, S_LOAD, nP_LOAD
High Current
M5, XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, XTAL_SEL, VCO_SEL
V
OH
V
OL
Output
High Voltage
Output
Low Voltage
TEST; NOTE 1
TEST; NOTE 1
Test Conditions
Minimum
2
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
I
IH
I
IL
Input
Low Current
-150
2. 6
0.5
µA
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
/2. See “Parameter Measurement Information” section,
“3.3V Output Load Test Circuit” figure.
8432CY-11
www.icst.com/products/hiperclocks.html
5
REV. E MAY 20, 2005
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