Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
•
4 differential 3.3V LVPECL outputs
•
Selectable CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, HSTL, SSTL, HCSL
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
Maximum output frequency up to 650MHz
•
Translates any single-ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 150ps (maximum)
•
Propagation delay: 1.4ns (maximum)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8533-01 is a low skew, high perfor-
mance 1-to-4 Differential-to-3.3V LVPECL fanout
HiPerClockS™
buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
The ICS8533-01 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL, CML,
or SSTL input levels. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8533-01 ideal for those applications demanding
well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK
nCLK
PCLK
nPCLK
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
CLK_SEL
ICS8533-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
8533AG-01
www.icst.com/products/hiperclocks.html
1
REV. B JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Type
Power
Input
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
Name
V
EE
CLK_EN
Negative supply pin. Connect to ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
Pullup
input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential PCLK, nPCLK
Pulldown inputs. When LOW, selects CLK, nCLK inputs.
LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Pullup
Inver ting differential clock input.
Inver ting differential LVPECL clock input.
No connect.
Positive supply pins. Connect to 3.3V.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
3
4
5
6
7
8, 9
10, 13, 18
11, 12
14, 15
16, 17
19, 20
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
V
CC
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Unused
Power
Output
Output
Output
Output
NOTE:
Pullup
and
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
CLK, nCLK
Input Capacitance
PCLK, nPCLK
CLK_EN, CLK_SEL
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum Typical
Maximum
4
4
4
Units
pF
pF
pF
KΩ
KΩ
8533AG-01
www.icst.com/products/hiperclocks.html
2
REV. B JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Inputs
Outputs
Selected Source
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
Q0 thru Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0 thru nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
CLK_EN
0
0
1
CLK_SEL
0
1
0
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Disabled
nCLK, nPCLK
CLK, PCLK
Enabled
CLK_EN
nQ0 - nQ3
Q0 - Q3
F
IGURE
1 - CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
nCLK or nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
LOW
HIGH
LOW
HIGH
HIGH
Outputs
Q0 thru Q3
nQ0 thru nQ3
HIGH
LOW
HIGH
LOW
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information section on page 8, Figure 8, which discusses wiring the differential
input to accept single ended levels.
8533AG-01
www.icst.com/products/hiperclocks.html
3
REV. B JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
73.2°C/W (0lfpm)
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these condition or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
=3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
=3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_EN, CLK_SEL
CLK_EN, CLK_SEL
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
3.765
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
=3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
8533AG-01
www.icst.com/products/hiperclocks.html
4
REV. B JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Test Conditions
PCLK
nPCLK
PCLK
nPCLK
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.3
V
EE
+ 1.5
V
CC
- 1.4
V
CC
- 2.0
1
V
CC
V
CC
- 1.0
V
CC
- 1.7
0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
V
V
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
Input High Current
Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
V
SWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Par t-to-Par t Skew; NOTE 3, 5
Cycle to Cycle Jitter ; NOTE 4, 5
Output Rise Time
Output Fall Time
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
IJ 650MHz
1.0
Test Conditions
Minimum
Typical
Maximum
650
1.4
30
150
150
700
700
53
Units
MHz
ns
ps
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
jit(cc)
t
R
t
F
odc
Output Duty Cycle
47
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8533AG-01
www.icst.com/products/hiperclocks.html
5
REV. B JULY 16, 2001
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