Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
•
4 differential 3.3V LVPECL outputs
•
Selectable CLK, nCLK or crystal inputs
•
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency up to 650MHz
•
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 150ps (maximum)
•
Propagation delay: 2ns (maximum)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS8533-11 is a low skew, high performance
1-to-4 Crystal Oscillator/Differential-to-3.3V
HiPerClockS™
LVPECL fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8533-11 has select-
able differential clock or crystal inputs. The CLK, nCLK pair
can accept most standard differential input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8533-11 ideal for those applications demand-
ing well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK
nCLK
XTAL1
XTAL2
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
CLK_SEL
ICS8533-11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92 Package Body
G Package
Top View
8533AG-11
www.icst.com/products/hiperclocks.html
1
REV. D
JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8, 9
10, 13, 18
11, 12
14, 15
16, 17
19, 20
Name
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
V
CC
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Input
Input
Input
Unused
Power
Output
Output
Output
Output
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Type
Description
Negative supply pin. Connect to ground.
Synchroning clock enable. When HIGH, clock outputs follows clock
input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVCMOS / LVTTL interface levels.
Clock select input. When LOW, selects CLK, nCLK input.
When HIGH, selects XTAL input. LVCMOS / LVTTL interface levels.
Non-inver ting differential clock input.
Inver ting differential clock input.
Crystal oscillator input.
Crystal oscillator input.
No connect.
Positive supply pins. Connect to 3.3V.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
NOTE:
Pullup
and
Pulldown
refers to internal input resistors. See Table 2, Pin characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
CLK, nCLK
CLK_EN, CLK_SEL
51
51
Test Conditions
Minimum
Typical
Maximum
4
4
Units
pF
pF
KΩ
KΩ
Input Pullup Resistor
Input Pulldown Resistor
REV. D
JULY 16, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Inputs
Outputs
Selected Source
CLK, nCLK
XTAL1, XTAL2
CLK, nCLK
Q0 thru Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0 thru nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
CLK_EN
0
0
1
CLK_SEL
0
1
0
1
1
XTAL1, XTAL2
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled folowing a rising and falling input clock or
crystal oscillator edge as shown in
Figure 1
.
In the active mode, the state of the outputs are a function of the CLK, nCLK and XTAL1, XTAL2 inputs as described
in Table 3B.
nCLK
CLK
Disabled
Enabled
CLK_EN
nQ0 - nQ3
Q0 - Q3
F
IGURE
1 - CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
LOW
HIGH
LOW
HIGH
HIGH
Outputs
Q0 thru Q3
nQ0 thru nQ3
HIGH
LOW
HIGH
LOW
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1:Please refer to the Application Information section on page 10, Figure 12, which discusses wiring the differential
input to accept single ended levels.
8533AG-11
www.icst.com/products/hiperclocks.html
3
REV. D
JULY 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
73.2°C/W (0lfpm)
-65°C to 150°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_EN,
CLK_SEL
CLK_EN,
CLK_SEL
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
Test Conditions
Minimum
2
-0.3
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-150
-5
Typical
Maximum
3.765
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
1.3
V
CC
- 0.85
Minimum Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
V
EE
+ 0.5
NOTE 1, 2
NOTE1: For single ended applications the maximum input voltage for CLK and nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
REV. D
JULY 16, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 1.0
V
CC
- 1.7
0.85
Units
V
V
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency Tolerance
Frequency Stability
Drive Level
Equivalent Series Resistance (ESR)
Shunt Capacitance
Series Pin Inductance
Operating Temperature Range
Aging
Frequency Range
Per year @ 25°C
3
0
-5
14
50
-50
-100
0.1
80
7
7
70
5
25
Test Conditions
Minimum Typical
Maximum
50
100
Units
ppm
ppm
mW
Ω
pF
nH
°C
ppm
MHz
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Maximum Input Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Par t-to-Par t Skew; NOTE 3, 5
Output Rise Time
Output Fall Time
Output Duty Cycle; NOTE 4
20% to 80% @ 50MHz
20% to 80% @ 50MHzz
300
300
47
50
IJ 650MHz
1.0
Test Conditions
Minimum
Typical
Maximum
650
2.0
30
150
700
700
53
Units
MHz
ns
ps
ps
ps
ps
%
ppm
t
sk(o)
t
sk(pp)
t
R
t
F
odc
oscTOL
Crystal Oscillator Tollerance
TBD
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Measured using CLK. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8533AG-11
www.icst.com/products/hiperclocks.html
5
REV. D
JULY 16, 2001
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