Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
F
EATURES
•
High speed differential multiplexer.
The device can be configured as a 2:1 multiplexer
•
Dual 3.3V LVPECL outputs
•
Selectable differential CLKxx, nCLKxx inputs
•
CLKxx, nCLKxx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency: 900MHz (typical)
G
ENERAL
D
ESCRIPTION
The ICS85356I is a dual 2:1 Differential-to-LVPECL
Multiplexer and is a member of the HiPerClockS
TM
HiPerClockS™
family of High Performance Clock Solutions from
ICS. The device has both common select and indi-
vidual select inputs. When COM_SEL is logic High,
the CLKxx input pairs will be passed to the output. When
COM_SEL is logic Low, the output is determined by the setting
of the SEL0 pin for channel 0 and the SEL1 pin for Channel 1.
ICS
The differential input has a common mode range that can accept
most differential input types such as LVPECL, LVDS, LVHSTL,
SSTL, and HCSL. The ICS85356I can therefore be used as a
differential translator to translate almost any differential input type
to LVPECL. It can also be used in ECL mode by setting V
CC
=0V
and V
EE
to -3.0V to - 3.8V.
The ICS85356I adds negligible jitter to the input clock and can
operate at high frequencies in excess of 900MHz thus making
it ideal for use in demanding applications such as SONET,
Fibre Channel, 1 Gigabit/10 Gigabit Ethernet.
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLKxx input
•
Output skew: 75ps (typical)
•
Propagation delay: 1.15ns (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.8V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3V to -3.8V
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package available
•
Compatible with MC100LVEL56
B
LOCK
D
IAGRAM
CLK0A
nCLK0A
CLK0B
nCLK0B
SEL0
COM_SEL
SEL1
0
1
Q0
nQ0
P
IN
A
SSIGNMENT
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
nc
CLK1B
nCLK1B
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
nQ0
SEL0
COM_SEL
SEL1
V
CC
Q1
nQ1
V
EE
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
nc
CLK1B
nCLK1B
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
nQ0
SEL0
COM_SEL
SEL1
V
CC
Q1
nQ1
V
EE
ICS85356I
CLK1A
nCLK1A
CLK1B
nCLK1B
0
1
Q1
nQ1
ICS85356I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
G Package
Top View
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm
M Package
Top View
85356AMI
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 7, 2004
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
Type
Power
Input
Input
Unused
Input
Input
Input
Input
Input
Input
Power
Output
Input
Input
Input
Output
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Description
Core supply pin.
Non-inver ting differential clock input.
Inver ting differential clock input.
No connect.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Negative supply pins.
Differential output pairs. LVPECL interface levels.
Clock select input. LVCMOS / LVTTL interface levels.
Common select input. LVCMOS / LVTTL interface levels.
Clock select input. LVCMOS / LVTTL interface levels.
Differential output pairs. LVPECL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
14, 20
1
2
3, 8
4
5
6
7
9
10
11
12, 13
15
16
17
18, 19
Name
V
CC
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
CLK1B
nCLK1B
V
EE
nQ1, Q1
SEL1
COM_SEL
SEL0
nQ0, Q0
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
COM_SEL
0
0
0
0
1
SEL1
0
0
1
1
X
SEL0
0
1
0
1
X
Q0
CLK0A
CLK0B
CLK0A
CLK0B
CLK0B
nQ0
nCLK0A
nCLK0B
nCLK0A
nCLK0B
nCLK0B
Outputs
Q1
CLK1A
CLK1A
CLK1B
CLK1B
CLK1B
nQ1
nCLK1A
nCLK1A
nCLK1B
nCLK1B
nCLK1B
85356AMI
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 7, 2004
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
46.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
40
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL0, SEL1, COM_SEL
SEL0, SEL1, COM_SEL
SEL0, SEL1
COM_SEL
SEL0, SEL1
COM_SEL
V
CC
= V
IN
= 3.6V
V
CC
= V
IN
= 3.6V
V
CC
= 3.6V, V
IN
= 0V
V
CC
= 3.6V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
Parameter
CLK0A, CLK0B,
CLK1A, CLK1B
Test Conditions
V
CC
= V
IN
= 3.6V
V
CC
= V
IN
= 3.6V
V
CC
= 3.6V, V
IN
= 0V
V
CC
= 3.6V, V
IN
= 0V
-5
-150
0.15
V
EE
+ 0.5
1.0
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
I
IH
I
IL
V
PP
V
CMR
nCLK0A, nCLK0B,
nCLK1A, nCLK1B
CLK0A, CLK0B,
CLK1A, CLK1B
Input Low Current
nCLK0A, nCLK0B,
nCLK1A, nCLK1B
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1, 2
Input High Current
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is V
CC
+ 0.3V.
85356AMI
www.icst.com/products/hiperclocks.html
3
REV. A OCTOBER 7, 2004
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
IJ 700MHz
0.6
Typical
Maximum
V
CC
- 1.0
V
CC
- 1.7
1.0
Units
V
V
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Output Rise Time
Output Fall Time
Duty Cycle Skew
20% to 80%
20% to 80%
200
200
IJ 900MHz
0.85
Test Conditions
Minimum
Typical
900
1.15
75
1.45
150
580
580
100
Maximum
Units
MHz
ns
ps
ps
ps
ps
t
sk(o)
t
R
t
F
t
odc
All parameters measured at ƒ
≤
622MHz unless noted otherwise.
This par t does not add measurable jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85356AMI
www.icst.com/products/hiperclocks.html
4
REV. A OCTOBER 7, 2004
Integrated
Circuit
Systems, Inc.
ICS85356I
2:1, D
IFFERENTIAL
-
TO
-3.3V
D
UAL
LVPECL / ECL C
LOCK
M
ULTIPLEXER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
V
CC
Qx
SCOPE
V
CC
LVPECL
V
EE
nQx
nCLKxA,
nCLKxB
V
CLKxA,
CLKxB
V
EE
PP
Cross Points
V
CMR
-1.3V ± 0.165V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
nQx
Qx
nQy
Qy
nCLKxA,
nCLKxB
CLKxA,
CLKxB
nQ0, nQ1
Q0, Q1
t
sk(o)
t
PD
O
UTPUT
S
KEW
P
ROPAGATION
D
ELAY
nQ0, nQ1
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
odc =
t
PW
t
PERIOD
Q0, Q1
Pulse Width
t
PERIOD
20%
O
UTPUT
R
ISE
/F
ALL
T
IME
85356AMI
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 7, 2004
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