Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
¸
1,
¸
2
C
LOCK
G
ENERATOR
F
EATURES
• 20 LVCMOS outputs, 7
W
typical output impedance
• Output frequency up to 250MHz
• 200ps bank skew, 250ps output skew, 300ps multiple
frequency skew, 600ps part-to-part skew
• LVCMOS / LVTTL clock input
• LVCMOS control inputs
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
• -40°C to 85°C ambient operating temperature
• Other divide values available on request
G
ENERAL
D
ESCRIPTION
The ICS8701I is a low skew, ÷1, ÷2 Clock Gen-
,&6
erator and a member of the HiPerClockS™
HiPerClockS™
family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS out-
puts are designed to drive 50
W
series or par-
allel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the
outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also con-
trols the active and high impedance states of all outputs.
The ICS8701I is characterized at 3.3V and mixed 3.3V in-
put supply, and 2.5V output supply operating modes. Guar-
anteed bank, output and part-to-part skew characteristics
make the ICS8701I ideal for those clock distribution appli-
cations demanding well defined performance and repeat-
ability.
B
LOCK
D
IAGRAM
LVCMOS_CLK
P
IN
A
SSIGNMENT
GND
QB2
GND
QB3
VDDO
QB4
QC0
VDDO
QC1
GND
QC2
GND
¸
1
¸
2
1
QAO - QA4
0
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
DIV_SELA
1
QB0 - QB4
0
DIV_SELB
1
QC0 - QC4
0
DIV_SELC
1
QD0 - QD4
0
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
Bank Enable
Logic
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23
24
ICS8701I
QB1
VDDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
VDDO
QA0
8701I
www.icst.com/products/hiperclocks.html
1
DIV_SELA
DIV_SELB
LVCMOS_CLK
GND
VDDI
BANK_EN0
GND
BANK_EN1
VDDI
nMR/OE
DIV_SELC
DIV_SELD
48-Pin LQFP
Y Package
Top View
REV. A MARCH 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
¸
1,
¸
2
C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
2, 5,
11, 26,
32, 35,
41, 44
7, 9, 18,
21, 28, 30,
37, 39, 46,
48
16, 20
25, 27,
29,
31, 33
34, 36,
38,
40, 42
43, 45,
47,
1, 3
4, 6,
8,
10, 12
22
13
14
23
24
17, 19
15
Name
VDDO
Power
Type
Description
Output power supply. Connect to 3.3V or 2.5V.
GND
VDDI
QA0, QA1,
QA2,
QA3, QA4
QB0, QB1,
QB2,
QB3, QB4
QC0, QC1,
QC2,
QC3, QC4
QD0, QD1,
QD2,
QD3, QD4
LVCMOS_CLK
DIV_SELD
DIV_SELC
DIV_SELB
DIV_SELA
BANK_EN1,
BANK_EN0
nMR/OE
Power
Power
Output
Ground. Connect to ground.
Input power supply. Connect to 3.3V.
Bank A outputs. LVCMOS interface levels.
7
W
typical output impedance.
Bank B outputs. LVCMOS interface levels.
7
W
typical output impedance.
Bank C outputs. LVCMOS interface levels.
7
W
typical output impedance.
Bank D outputs. LVCMOS interface levels
7
W
typical output impedance.
Pulldown Clock input. LVCMOS interface levels.
Controls frequency division for bank D outputs.
Pullup
LVCMOS interface levels.
Controls frequency division for bank C outputs.
Pullup
LVCMOS interface levels.
Controls frequency division for bank B outputs.
Pullup
LVCMOS interface levels.
Controls frequency division for bank A outputs.
Pullup
LVCMOS interface levels.
Pullup
Pullup
Enables and disables outputs by banks. LVCMOS interface levels.
Master reset and output enable. Enables and disables all outputs.
LVCMOS interface levels.
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
8701I
www.icst.com/products/hiperclocks.html
2
REV. A MARCH 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
¸
1,
¸
2
C
LOCK
G
ENERATOR
Maximum
Units
pF
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
Parameter
LVCMOS_CLK
DIV_SELA, DIV_SELB,
Input
DIV_SELC, DIV_SELD,
Capacitance
BANK_EN0, NMR/OE,
BANK_EN1,
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
VDDI, VDDO =
3.465V
VDDI = 3.465V,
VDDO = 2.625V
7
Test Conditions
Minimum Typical
CIN
RPULLUP
RPULLDOWN
CPD
51
51
K
W
pF
pF
K
W
ROUT
W
T
ABLE
3. F
UNCTION
T
ABLE
Inputs
nMR/OE
0
1
1
1
1
1
1
1
1
BANK_EN1
X
0
1
0
1
0
1
0
1
BANK_EN0
X
0
0
1
1
0
0
1
1
DIV_SELx
X
0
0
0
0
1
1
1
1
QA0 - QA4
Hi Z
Active
Active
Active
Active
Active
Active
Active
Active
QB0 - QB4
Hi Z
Hi Z
Active
Active
Active
Hi Z
Active
Active
Active
Outputs
QC0 - QC4
Hi Z
Hi Z
Hi Z
Active
Active
Hi Z
Hi Z
Active
Active
QD0 - QD4
Hi Z
Hi Z
Hi Z
Hi Z
Active
Hi Z
Hi Z
Hi Z
Active
Qx
frequency
zero
fIN/2
fIN/2
fIN/2
fIN/2
fIN
fIN
fIN
fIN
8701I
www.icst.com/products/hiperclocks.html
3
REV. A MARCH 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
¸
1,
¸
2
C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
-40°C to 85°C
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of product at these condition or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
VDDI=VDDO=3.3V±5%, T
A
=-40°C
TO
85°C
Symbol
VDDI
VDDO
IDD
Parameter
Input Power Supply Voltage
Output Power Supply Voltage
Quiescent Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
100
Units
V
V
mA
VDDI = VIH = 3.465V
VIL = 0V
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
VDDI=VDDO=3.3V±5%, T
A
=-40°C
TO
85°C
Symbol
Parameter
Input
High Voltage
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
BANK_EN1, nMR/OE
LVCMOS_CLK
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
BANK_EN1, nMR/OE
LVCMOS_CLK
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
BANK_EN1, nMR/OE
LVCMOS_CLK
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
BANK_EN1, nMR/OE
LVCMOS_CLK
Test Conditions
VDDI = 3.465V
VDDI = 3.465V
VDDI = 3.465V
VDDI = 3.465V
VDDI = VIN = 3.465V
VDDI = VIN = 3.465V
VDDI = 3.465V, VIN = 0V
VDDI = 3.465V, VIN = 0V
VDDI = VDDO = 3.135V
IOH = -36mA
VDDI = VDDO = 3.135V
IOL = 36mA
-150
-5
2.6
0.5
Minimum
2
2
-0.3
-0.3
Typical
Maximum
3.8
3.8
0.8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
VIH
VIL
Input
Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
VOH
VOL
Output High Voltage
Output Low Voltage
8701I
www.icst.com/products/hiperclocks.html
4
REV. A MARCH 16, 2001
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
¸
1,
¸
2
C
LOCK
G
ENERATOR
Maximum
250
0MHZ
£
f
£
200MHz
0MHZ
£
f
£
200MHz
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
30% to 70%
30% to 70%
0MHZ
£
f
£
200MHz
f = 200MHz
200
200
tCYCLE/2
- 0.6
1.9
2.2
2.2
3.6
3.6
200
250
300
600
900
900
tCYCLE/2
+ 0.6
3.1
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
T
ABLE
5A. AC C
HARACTERISTICS
,
VDDI=VDDO=3.3V±5%, T
A
=-40°C
TO
85°C
Symbol
fMAX
tpLH
tpHL
tsk(b)
tsk(o)
tsk(w)
tsk(pp)
tR
tF
tPW
tEN
Parameter
Maximum Input Frequency
Propagation Delay,
Low-to-High
Propagation Delay,
High-to-Low
Bank Skew; NOTE 2
Output Skew; NOTE 3
Multiple Frequency Skew;
NOTE 4
Par t to Par t Skew; NOTE 5
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
Output Pulse Width
Test Conditions
Minimum
Typical
tCYCLE/2
2.5
Output Enable Time;
f = 10MHz
6
NOTE 6
Output Disable Time;
tDIS
f = 10MHz
6
NOTE 6
NOTE 1: All parameters measured at 200MHz unless noted otherwise. All outputs terminated with 50
W
to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and
with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701I
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5
REV. A MARCH 16, 2001
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