Integrated
Circuit
Systems, Inc.
ICS9148-53
Frequency Generator & Integrated Buffers for Mother Boards
General Description
The
ICS9148-53
generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro, AMD or Cyrix. Sixteen different reference
frequency multiplying factors are externally selectable with
smooth frequency transitions.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The
ICS9148-53
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection. The
SDRAM12 output may be used as a feed back into an off chip
PLL.
Features
Generates the following system clocks:
- 3 CPU(2.5V/3.3V) up to 150MHz.
- 7 PCI(3.3V) (including one free
running PCICLK)
- 2AGP(3.3V) @ 2 x PCI
- 13 SDRAMs(3.3V) up to 150MHz
- 1 REF (3.3V) @ 14.318MHz
- 1 Fixed clock 3.3V @ 48MHz
Skew characteristics:
- CPU CPU<250ps
- CPU(early) PCI : 1-4ns
Supports Spread Spectrum modulation & I
2
C
programming for Power Management, Frequency Select
Efficient Power management scheme through power
down CPU, PCI, AGP and CPU_STOP clocks.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
Read back of FS pin values from I
2
C
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:12), supply for PLL core
VDD4 = AGP (1:2)
VDD5 = Fixed PLL, 48MHz , AGP0
VDDL = CPUCLK (0:3)
9148-53 Rev C 08/14/98
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-53
Pin Descriptions
PIN NUMBER
1
2
3,9,16,22,27,
33,39,45
4
5
6
7
FS1
1, 2
8
10, 11, 12, 13, 47
14
15
17
PCICLK0
FS2
1, 2
PCICLK(1:5)
VDD5
BUFFERIN
CPU_STOP#
SDRAM 11
18
28, 29, 31, 32, 34,
35,37,38
20
PCI_STOP#
1
SDRAM 10
SDRAM (0:9)
AGP_STOP#
1
SDRAM9
21
19,30,36
23
24
25
MODE
1, 2
48MHz
26
41, 43, 44
40
42
46
48
FS0
1, 2
CPUCLK(0:3)
SDRAM12
VDDL
AGP1
VDD4
IN
OUT
IN
OUT
OUT
PWR
OUT
PWR
PD#
1
SDRAM8
VDD3
SDATA
SCLK
AGP0
IN
OUT
IN
OUT
PWR
IN
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
PWR
IN
IN
OUT
PIN NAME
VDD1
REF0
FS3
GND
X1
X2
VDD2
PCICLK_F
TYPE
PWR
OUT
IN
PWR
IN
OUT
PWR
OUT
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Supply for fixed PLL, 48MHz, AGP0
Input pin for SDRAM buffers.
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile
Mode, MODE=0)
SDRAM clock output
Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode,
MODE=0)
SDRAM clock output
SDRAM clock outputs.
This asynchronous input halts AGP(1:2) clocks at logic "0" level when input
low (in Mobile Mode, MODE=0) Does not affect AGP0
SDRAM clock output
This asyncheronous Power Down input Stops the VCO, crystal & internal
clocks when active, Low. (In Mobile Mode, MODE=0)
SDRAM clock output
Supply for SDRAM (0:11), CPU Core, 48MHz clocks,
nominal 3.3V.
Data input for I
2
C serial input.
Clock input of I
2
C input
Advanced Graphic Port output, powered by VDD4. Not affected by
AGP_STOP#
Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock for USB timing.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Feedback SDRAM clock output.
Supply for CPU (0:3), either 2.5V or 3.3V nominal
Advanced Graphic Port output powered by VDD4.
Supply for AGP (0:2)
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
ICS9148-53
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
0
1
Pin 17
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
Pin 18
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
Pin 20
AGP_STOP#
(INPUT)
SDRAM 9
(OUTPUT)
Pin 21
PD#
(INPUT)
SDRAM 8
(OUTPUT)
Power Management Functionality
AGP_STOP# CPU_STOP#
1
1
1
0
0
1
1
1
PCI_STOP#
1
1
0
1
AGP,
CPUCLK
Outputs
Stopped Low
Running
Running
Running
PCICLK
(0:5)
Running
Running
Stopped Low
Running
PCICLK_F,
REF, 48MHz
and SDRAM
Running
Running
Running
Running
Crystal
OSC
Running
Running
Running
Running
VCO
Running
Running
Running
Running
AGP(1:2)
Running
Running
Running
Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Input level
(Latched Data)
1
0
Buffer Selected for
operation at:
2.5V VDD
3.3V VDD
3
ICS9148-53
Functionality
V
DD
1, 2, 3, 4 = 3.3V±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FS2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
FS1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU,SDRAM
(MHZ)
133
124
150
140
105
112
115
120
100
95.25
83.3
75
75
68.5
66.8
60
REF, IOAPIC
PCI (MHZ) AGP (MHZ)
(MHZ)
44.33
88.67
14.318
41.33
82.67
14.318
50
100
14.318
46.67
93.33
14.318
35
70
14.318
37.33
74.67
14.318
38.33
76.66
14.318
40
80
14.318
33.3
66.6
14.318
31.75
63.5
14.318
33.3
66.6
14.318
30
60
14.318
37.5
75
14.318
34.25
68.5
14.318
33.4
66.8
14.318
30
60
14.318
4
ICS9148-53
General I
2
C serial interface information
A.
Clock Generator
Address (7 bits)
For the clock generator to be addressed by an I
2
C controller, the following address must be sent as a start sequence, with
an acknoledge bit between each byte.
A(6:0) & R/W#
D2
(H)
B.
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
The clock generator is a slave/receiver I
2
C component. It can read back the data stored in the latches for verification. (set
R/W# to 1 above)
Read-Back will support Intel PIIX4 "Block-Read" protocol,
with a "Byte count" following the
address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D3
(H)
C.
D.
E.
F.
ACK
Byte Count
Readback
ACK
Then Byte 0, 1, 2, etc. in
sequence until STOP.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only
"Block Writes"
from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
The Fixed clocks 48MHz and 24MHz are not addressable in the registers for Stopping. These output are always running,
except in Tristate Mode.
At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1
(Enabled output state).
G
.
H.
5
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