Integrated
Circuit
Systems, Inc.
ICS9248- 81
Frequency Generator & Integrated Buffers
General Description
The
ICS9248-81
is the single chip clock solution for Desktop/
Notebook designs using the SIS style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The
ICS9248-81
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the
CPUCLK frequency(SD_SEL=1) or other clock frequencies
(SD_SEL=0)
Features
Generates the following system clocks:
- 3 CPU(2.5V/3.3V) up to 133.3MHz.
- 6 PCI(3.3V) (including 1 free-running)
- 13 SDRAMs(3.3V) up to 133.3MHz.
- 3 REF (3.3V) @ 14.318MHz
- 1 clock @ 24/14.3 MHz selectable output for SIO
- 1 Fixed clock at 48MHz (3.3V)
- 1 IOAPIC @ 2.5V / 3.3V
Skew characteristics:
- CPU CPU<175ps
- SDRAM SDRAM < 250ps
- CPUSDRAM < 500ps
- CPU(early) PCI : 1-4ns (typ. 3ns)
- PCI PCI <500ps
Supports Spread Spectrum modulation ±0.25 & ±0.5%
center spread
Serial I
2
C interface for Power Management, Frequency
Select, Spread Spectrum.
Efficient Power management scheme through PCI,
SDRAM, CPU STOP CLOCKS and PD#.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
Block Diagram
Pin Configuration
Power Groups
VDDREF = REF [2:0], X1, X2
VDDPCI = PCICLK_F, PCICLK [4:0]
VDDSD/C = SDRAM [11:0], supply for PLL core, 24 MHz, 48MHz
VDD/CPU = CPUCLK [3:1]
VDDLAPIC = IOAPIC
GNDFIX = Ground for fixed clock PLL and output buffers
9248-81 Rev E 10/12/99
48-Pin SSOP
* Internal Pull-up Resistor of
120K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248 -81
Pin Descriptions
Pin number
1
2
1,2
3,9,16,22,
27,33,39
4
5
6,14
7
1,2
8
1,2
13, 12, 11, 10
15,28,29,31,32,
34,35,37,38
17
1
Pin name
VDDR/X
REF0
Mode
GND
X1
X2
VDDPCI
FS1
PCICLK_F
PCICLK 0
FS2
PCICLK [4:1]
SDRAM 12,
SDRAM [7:0]
SDRAM 11
CPU_STOP#
SDRAM 10
Type
Power
Output
Input
Power
Input
Output
Power
Input
Output
Output
Input
Output
Output
Output
Input
Output
Input
Power
Output
Input
Output
Input
Input
Input
Input
Output
Input
Output
Power
0utput
Power
Output
Input
Power
Output
Input
Output
Power
Description
Isolated 3.3 V power for crystal & reference
3.3V, 14.318 MHz reference clock output.
Function select pin, 1=desk top mode, 0=mobile mode. Latched input.
3.3 V Ground
14.318 MHz crystal input
14.318 MHz crystal output
3.3 V power for the PCI clock outputs
Logic input frequency select bit. Input latched at power-on.
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
3.3 V PCI clock outputs, generating timing requirements for Pentium II
Logic input frequency select bit. Input latched at power-on.
3.3 V PCI clock outputs, generating timing requirements for Pentium II
SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
Asynchronous active low input pin used to stop the CPUCLK in low state,
all other clocks will continue to run. The CPUCLK will have a "Turnon" latency
of at least 3 CPU clocks.
SDRAM clock outputs. Frequency is selected by SD-SEL latched input.
Synchronous active low input used to stop the PCICLK in a low state. It will not
effect PCICLK_F or any other outputs.
3.3 V power for SDRAM outputs and core
SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
Asynchronous active low input used to stop the SDRAM in a low state.
It will not effect any other outputs.
SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Data input for I
2
C serial input.
Clock input of I
2
C input
This input pin controls the frequency of the SIO. If logic 0 at power on
SIO=14.318 MHz . If logic 1 at power-on SIO=24MHz.
Super I/O output. 24 or 14.318 MHz. Selectable at power-up by SEL24_14MHz
Logic input frequency select bit. Input latched at power-on.
3.3 V 48 MHz clock output, fixed frequency clock typically used with
USB devices
3.3 V power for SDRAM outputs
2.5 V CPU and Host clock outputs
2.5 V power for CPU
3.3V, 14.318 MHz reference clock output.
This pin selects the operating voltage for the CPU. If logic 0 at power on
CPU=3.3 V and if logic 1 at power on CPU=2.5 V operating voltage.
2.5 V Ground for the IOAPIC or CPU
3.3V, 14.318 MHz reference clock output.
This input pin controls the frequency of the SDRAM.
2.5V fixed 14.318 MHz IOAPIC clock outputs
2.5 V power for IOAPIC
18
1
PCI-STOP#
VDDSD/C
SDRAM 9
SDRAM_STOP#
SDRAM 8
19
20
1
21
1
23
24
25
1,2
PD#
SDATA
SCLK
SEL24_14#
SIO
FS0
26
1,2
48 MHz
VDDSDR
CPUCLK [3:1]
VDDLCPU
REF2
CPU3.3#_2.5
GNDL
REF1
SD_SEL
IOAPIC
VDDLAPIC
30,36
40,41,43
42
44
1,2
45
46
1,2
47
48
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2
ICS9248-81
Mode Pin - Power Management Input Control
MODE, Pin 2
(Latched Input)
0
1
Pin 17
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
Pin 18
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
Pin 20
SDRAM_STOP#
(INPUT)
SDRAM9
(OUTPUT)
Pin 21
PD#
(INPUT)
SDRAM8
(OUTPUT)
Power Management Functionality
PD#
CPU_STOP# PCI_STOP# SDRAM_STOP
PCICLK
(0:4)
SDRAM
(0:12)
PCICLK_F
CPUCLK
Crystal
OSC
VCO
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
0
0
X
1
1
0
0
1
1
0
0
X
1
0
1
0
1
0
1
0
Stopped
Low
Running
Running
Stopped
Low
Stopped
Low
Running
Running
Stopped
Low
Stopped
Low
Stopped
Low
Running
Stopped
Low
Running
Stopped
Low
Running
Stopped
Low
Running
Stopped
Low
Stopped
Low
Running
Running
Running
Running
Running
Running
Running
Running
Stopped
Low
Running
Running
Running
Running
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Running
Running
Running
Running
Running
Running
Running
Running
Stopped
Low
Running
Running
Running
Running
Running
Running
Running
Running
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Input level
(Latched Data)
Buffer Selected
for operation at:
2.5V VDD
3.3V VDD
1
0
3
ICS9248 -81
Functionality
V
DD
1, 2, 3, 4 = 3.3V±5%, V
DDL
= 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
CPU
MHZ
90.00
66.70
95.00
100.00
100.00
112.00
124.00
133.30
66.70
75.00
83.30
95.00
100.00
112.00
124.00
133.30
SDRAM
MHZ
90.00
100.05
63.33
66.66
75.00
74.66
82.66
88.86
66.70
75.00
83.30
95.00
100.00
112.00
124.00
133.30
PCI
MHZ
30.00
33.35
31.66
33.33
30.00
37.33
31.00
33.32
33.35
30.00
33.32
31.66
33.33
37.33
31.00
33.33
REF, IOAPIC
MHZ
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
SD_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4
ICS9248-81
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will
acknowledge
each byte
one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
ACK
Stop Bit
ACK
Byte 5
ACK
Byte 4
ACK
Byte 3
ACK
Byte 2
ACK
Byte 1
ACK
Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
5
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