5962-8956809VTC datasheet, PDF

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5962-8956809VTC: DescriptionFIFO, 4KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28; Categorystorage storage; File Size2MB，20 Pages; Manufacturere2v technologies

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5962-8956809VTC Overview

FIFO, 4KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28

5962-8956809VTC Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	DIP
package instruction	DIP,
Contacts	28
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	30 ns
Other features	RETRANSMIT
period time	40 ns
JESD-30 code	R-CDIP-T28
JESD-609 code	e4
length	27.94 mm
memory density	36864 bit
memory width	9
Number of functions	1
Number of terminals	28
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	4KX9
Exportable	NO
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	3.94 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm
Base Number Matches	1

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Features

•

First-in First-out Dual Port Memory

4096-bit x 9 Organization

Fast Flag and Access Times: 15, 30 ns

Wide Temperature Range: -55°C to +125°C

Fully Expandable by Word Width or Depth

Asynchronous Read/Write Operations

Empty, Full and Half Flags in Single Device Mode

Retransmit Capability

Bi-directional Applications

Battery Backup Operation: 2V Data Retention

TTL Compatible

Single 5V ± 10% Power Supply

No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm

Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019

Quality grades : QML Q and V with SMD 5962-89568 and ESCCwith specification

9301/049

Rad. Tolerant

High Speed

4 Kb x 9

Parallel FIFO

M67204H

Description

The M67204H implements a first-in first-out algorithm, featuring asynchronous

read/write operations. The FULL and EMPTY flags prevent data overflow and under-

flow. The expansion logic allows unlimited expansion in word size and depth with no

timing penalties. Twin address pointers automatically generate internal read and write

addresses, and no external address information is required for the Atmel FIFOs.

address pointers are automatically incremented with the write pin and read pin. The 9

bits wide data are used in data communications applications where a parity bit for

error checking is necessary. The retransmit pin reset the read pointer to zero without

affecting the write pointer. This is very useful for retransmitting data when an error is

detected in the system.

Using an array of eight transistors (8T) memory cell, the M67204H combines an

extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns

over the full temperature range. All versions offer battery backup data retention capa-

bility with a typical power consumption at less than 2 µW.

The M67204H is processed according to the methods of the latest revision of the MIL

PRF 38535 (Q and V) or ESCC 9000.

4141J–AERO–04/07

Write Enable (W)

A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

Data set-up and hold times must be maintained in the rise time of the leading edge of

the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) will be set to low and remain in this state until the difference

between the write and read pointers is less than or equal to half of the total available

memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the

read operation.

To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-

tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked from W, so that external changes to W will have no effect on the full FIFO stack.

Read Enable (R)

A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not with

standing any current write operations. After Read Enable (R) goes high, the Data Out-

puts (Q0 - Q8) will return to a high impedance state until the next Read operation. When

all the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing

the “final” read cycle, but inhibiting further read operations whilst the data outputs

remain in a high impedance state. Once a valid write operation has been completed, the

Empty Flag (EF) will go high after tWEF and a valid read may then be initiated. When

the FIFO stack is empty, the internal read pointer is blocked from R, so that external

changes to R will have no effect on the empty FIFO stack.

This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground to indicate that it is the first loaded (see Operating Modes). In the Single Device

Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-

necting the Expansion In (XI) to ground.

The M67204H can be made to retransmit data when the Retransmit Enable Control (RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the high state during retransmit. The retransmit feature is intended for use when a

number of writes equals to or less than the depth of the FIFO has occured since the last

RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode and

will affect the Half-Full Flag (HF), in accordance with the relative locations of the read

and write pointers.

First Load/Retransmit

(FL/RT)

Expansion In (XI)

This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an

operation in the single device mode. Expansion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Daisy Chain modes.

The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is

one location less than the read pointer, indicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 4096 writes.

The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating that the device is empty.

Full Flag (FF)

Empty Flag (EF)

M67204H

4141J–AERO–04/07

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