APEX 20KC
®
Programmable Logic
Device
Data Sheet
February 2004 ver. 2.2
Features...
■
■
Programmable logic device (PLD) manufactured using a 0.15-µm all-
layer copper-metal fabrication process
–
25 to 35% faster design performance than APEX
TM
20KE devices
–
Pin-compatible with APEX 20KE devices
–
High-performance, low-power copper interconnect
–
MultiCore
TM
architecture integrating look-up table (LUT) logic
and embedded memory
–
LUT logic used for register-intensive functions
–
Embedded system blocks (ESBs) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
High-density architecture
–
200,000 to 1 million typical gates (see
Table 1)
–
Up to 38,400 logic elements (LEs)
–
Up to 327,680 RAM bits that can be used without reducing
available logic
Note (1)
EP20K400C
1,052,000
400,000
16,640
104
212,992
4
-7, -8, -9
1,664
488
Table 1. APEX 20KC Device Features
Feature
Maximum system gates
Typical gates
LEs
ESBs
Maximum RAM bits
PLLs
(2)
Speed grades
(3)
Maximum macrocells
Maximum user I/O pins
Notes to
Table 1:
(1)
(2)
(3)
EP20K200C
526,000
200,000
8,320
52
106,496
2
-7, -8, -9
832
376
EP20K600C
1,537,000
600,000
24,320
152
311,296
4
-7, -8, -9
2,432
588
EP20K1000C
1,772,000
1,000,000
38,400
160
327,680
4
-7, -8, -9
2,560
708
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
PLL: phase-locked loop.
The -7 speed grade provides the fastest performance.
Altera Corporation
DS-APEX20KC-2.2
1
APEX 20KC Programmable Logic Device Data Sheet
...and More
Features
■
■
■
Low-power operation design
–
1.8-V supply voltage (see
Table 2)
–
Copper interconnect reduces power consumption
–
MultiVolt
TM
I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces
–
ESBs offering programmable power-saving mode
Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
–
Built-in low-skew clock tree
–
Up to eight global clock signals
–
ClockLock
TM
feature reducing clock delay and skew
–
ClockBoost
TM
feature providing clock multiplication and
division
–
ClockShift
TM
feature providing programmable clock phase and
delay shifting
Powerful I/O features
–
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG)
PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
–
Support for high-speed external memories, including DDR
synchronous dynamic RAM (SDRAM) and ZBT static RAM
(SRAM)
–
16 input and 16 output LVDS channels at 840 megabits per
second (Mbps)
–
Direct connection from I/O pins to local interconnect providing
fast
t
CO
and
t
SU
times for complex logic
–
MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces
–
Programmable clamp to V
CCIO
–
Individual tri-state output enable control for each pin
–
Programmable output slew-rate control to reduce switching
noise
–
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT,
SSTL-3 and SSTL-2, GTL+, and HSTL Class I
–
Supports hot-socketing operation
–
Pull-up on I/O pins before and during configuration
Table 2. APEX 20KC Supply Voltages
Feature
Internal supply voltage (V
CCINT
)
1.8 V
Voltage
MultiVolt I/O interface voltage levels (V
CCIO
) 1.8 V, 2.5 V, 3.3 V, 5.0 V
(1)
Note to
Table 2:
(1)
APEX 20KC devices can be 5.0-V tolerant by using an external resistor.
2
Altera Corporation
APEX 20KC Programmable Logic Device Data Sheet
■
■
Advanced interconnect structure
–
Copper interconnect for high performance
–
Four-level hierarchical FastTrack
®
interconnect structure
providing fast, predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
Advanced software support
–
Software design support and automatic place-and-route
provided by the Altera
®
Quartus
TM
II development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
–
Altera MegaCore
®
functions and Altera Megafunction Partners
Program (AMPP
SM
) megafunctions optimized for APEX 20KC
architecture available
–
NativeLink
TM
integration with popular synthesis, simulation,
and timing analysis tools
–
Quartus II SignalTap
®
embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
–
Supports popular revision-control software packages including
PVCS, RCS, and SCCS
Notes (1), (2)
652-Pin BGA
Table 3. APEX 20KC QFP & BGA Package Options & I/O Count
Device
EP20K200C
EP20K400C
EP20K600C
EP20K1000C
208-Pin PQFP 240-Pin PQFP
136
168
356-Pin BGA
271
488
488
488
Altera Corporation
3
APEX 20KC Programmable Logic Device Data Sheet
Table 4. APEX 20KC FineLine BGA Package Options & I/O Count
Notes (1), (2)
Device
EP20K200C
EP20K400C
EP20K600C
EP20K1000C
Notes to
Tables 3
and
4:
(1)
(2)
(3)
I/O counts include dedicated input and clock pins.
APEX 20KC device package types include plastic quad flat pack (PQFP), 1.27-mm
pitch ball-grid array (BGA), and 1.00-mm pitch FineLine BGA
TM
packages.
This device uses a thermally enhanced package, which is taller than the regular
package. Consult the
Altera Device Package Information Data Sheet
for detailed
package size information.
484 Pin
376
672 Pin
1,020 Pin
488
(3)
508
(3)
508
(3)
588
708
Table 5. APEX 20KC QFP & BGA Package Sizes
Feature
Pitch (mm)
Area (mm
2
)
Length
×
Width (mm
×
mm)
208-Pin PQFP
0.50
924
30.4
×
30.4
240-Pin PQFP
0.50
1,218
34.9
×
34.9
356-Pin BGA
1.27
1,225
35.0
×
35.0
652-Pin BGA
1.27
2,025
45.0
×
45.0
Table 6. APEX 20KC FineLine BGA Package Sizes
Feature
Pitch (mm)
Area (mm )
Length
×
Width (mm
×
mm)
2
484 Pin
1.00
529
23
×
23
672 Pin
1.00
729
27
×
27
1,020 Pin
1.00
1,089
33
×
33
General
Description
Similar to APEX 20K and APEX 20KE devices, APEX 20KC devices offer
the MultiCore architecture, which combines the strengths of LUT-based
and product-term-based devices with an enhanced memory structure.
LUT-based logic provides optimized performance and efficiency for data-
path, register-intensive, mathematical, or digital signal processing (DSP)
designs. Product-term-based logic is optimized for complex
combinatorial paths, such as complex state machines. LUT- and product-
term-based logic combined with memory functions and a wide variety of
MegaCore and AMPP functions make the APEX 20KC architecture
uniquely suited for SOPC designs. Applications historically requiring a
combination of LUT-, product-term-, and memory-based devices can now
be integrated into one APEX 20KC device.
4
Altera Corporation
APEX 20KC Programmable Logic Device Data Sheet
APEX 20KC devices include additional features such as enhanced I/O
standard support, CAM, additional global clocks, and enhanced
ClockLock clock circuitry.
Table 7
shows the features included in
APEX 20KC devices.
Table 7. APEX 20KC Device Features (Part 1 of 2)
Feature
MultiCore system integration
Hot-socketing support
SignalTap logic analysis
32-/64-bit, 33-MHz PCI
32-/64-bit, 66-MHz PCI
MultiVolt I/O
Full support
Full support
Full support
Full compliance
Full compliance in -7 and -8 speed grades in
selected devices
1.8-V, 2.5-V, or 3.3-V V
CCIO
V
CCIO
selected bank by bank
5.0-V tolerant with use of external resistor
Clock delay reduction
m
/(n
×
v)
clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift circuitry
LVDS support
Up to four PLLs
ClockShift clock phase adjustment
Eight
APEX 20KC Devices
ClockLock support
Dedicated clock and input pins
Altera Corporation
5
京公网安备 11010802033920号
EEWORLD
