LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life
support devices or systems unless a specific written agreement pertaining to such intended use is executed
between the manufacturer and an officer of PSC.
1) Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2) A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products
or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom Semiconductor does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The
Company makes no representations that circuitry described herein is free from patent infringement or
other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.
All other trademarks are of their respective companies.
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
TABLE OF CONTENTS
1
2
3
DESCRIPTION................................................................................................................................... 9
FEATURES ......................................................................................................................................... 9
SIGNAL DEFINITIONS.................................................................................................................. 10
3.1
SIGNAL TYPES ....................................................................................................................... 10
3.2
SIGNALS .................................................................................................................................. 10
3.2.1
PRIMARY BUS INTERFACE SIGNALS............................................................................... 10
3.2.2
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.......................................... 12
3.2.3
SECONDARY BUS INTERFACE SIGNALS......................................................................... 13
3.2.4
SECONDARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.................................... 14
3.2.5
CLOCK SIGNALS................................................................................................................. 15
3.2.6
STRAPPING PINS AND MISCELLANEOUS SIGNALS ...................................................... 16
3.2.7
JTAG BOUNDARY SCAN AND TEST SIGNALS ................................................................. 17
3.2.8
TEST SIGNALS..................................................................................................................... 18
3.2.9
POWER AND GROUND SIGNALS...................................................................................... 18
3.3
PIN LIST ................................................................................................................................... 19
4
PCI BUS OPERATION.................................................................................................................... 22
4.1
TYPES OF TRANSACTIONS.................................................................................................. 22
4.2
WRITE TRANSACTIONS ....................................................................................................... 23
4.2.1
MEMORY WRITE TRANSACTIONS .................................................................................... 23
4.2.1.1
4.2.1.2
4.2.1.3
4.2.1.4
PCI-X TO PCI-X ....................................................................................................................... 24
PCI TO PCI................................................................................................................................ 24
PCI TO PCI-X............................................................................................................................ 24
PCI-X TO PCI............................................................................................................................ 25
4.2.2
DELAYED/SPLIT WRITE TRANSACTIONS........................................................................ 25
4.2.3
IMMEDIATE WRITE TRANSACTIONS ............................................................................... 25
4.3
READ TRANSACTIONS ......................................................................................................... 25
4.3.1
MEMORY READ TRANSACTIONS...................................................................................... 26
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
PCI-X TO PCI-X ....................................................................................................................... 26
PCI TO PCI................................................................................................................................ 26
PCI TO PCI-X............................................................................................................................ 26
PCI-X TO PCI............................................................................................................................ 27
4.3.2
4.3.3
4.3.4
4.3.5
I/O READ.............................................................................................................................. 27
CONFIGURATION READ ................................................................................................... 27
TYPE 1 CONFIGURATION READ ......................................................................................... 27
TYPE 0 CONFIGURATION READ ......................................................................................... 27
4.3.3.1
4.3.3.2
NON-PREFETCHABLE AND DWORD READS.................................................................. 28
PREFETCHABLE READS.................................................................................................... 28
PCI-X TO PCI-X AND PCI-X TO PCI .................................................................................... 28
PCI TO PCI................................................................................................................................ 28
PCI TO PCI-X............................................................................................................................ 29
4.3.5.1
4.3.5.2
4.3.5.3
4.3.6
DYNAMIC PREFETCH (CONVENTIONAL PCI MODE ONLY) ........................................ 29
4.4
CONFIGURATION TRANSACTIONS ................................................................................... 29
4.4.1
TYPE 0 ACCESS TO PI7C21P100....................................................................................... 30
4.4.2
TYPE 1 TO TYPE 0 CONVERSION ..................................................................................... 30
4.4.3
TYPE 1 TO TYPE 1 FORWARDING.................................................................................... 31
4.4.4
SPECIAL CYCLES ............................................................................................................... 32
5
TRANSACTION ORDERING ........................................................................................................ 32
5.1
5.2
6
GENERAL ORDERING GUIDELINES................................................................................... 33
ORDERING RULES................................................................................................................. 33
CLOCKS............................................................................................................................................ 34
Page 5 of 77
June 10, 2005 Revision 1.06
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