K7R643682M
K7R641882M
K7R640982M
2Mx36 & 4Mx18 & 8Mx9 QDR
TM
II b2 SRAM
72Mb QDRII SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.3 March 2007
K7R643682M
K7R641882M
K7R640982M
Document Title
2Mx36 & 4Mx18 & 8Mx9 QDR
TM
II b2 SRAM
2Mx36-bit, 4Mx18-bit, 8Mx9-bit QDR
TM
II b2 SRAM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1. Update AC timing characteristics.
2. Change the JTAG instruction coding.
1. Change the AC timing characteristics. (-25/-20 parts)
2. Correct the overshoot and undershoot timing diagrams.
3. Change the JTAG Block diagrams.
4. Update the Boundary scan exit order.
1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
1. Add the Power-on Sequence specification
1. Correct the pin name table
1. Update the power consumption (Icc & Isb)
1. Finalize the datasheet
1. Add Pb-free comment
2. Change the Max. clock cycle time in AC TIMING CHARACTERIS-
TICS
1. Correct the pin name table
1. Add Detail Specification of Power up Sequence
Draft Date
Sep, 14 2002
Oct. 24, 2002
Remark
Advance
Preliminary
0.2
Feb. 18, 2003
Preliminary
0.3
Mar. 20, 2003
Preliminary
0.4
0.5
0.6
1.0
1.1
Aug. 16, 2004
Oct. 18, 2004
May. 17, 2005
Aug. 2, 2005
Jul. 6, 2006
Preliminary
Preliminary
Preliminary
Final
Final
1.2
1.3
Jan. 23, 2007
Mar. 5, 2007
Final
Final
-2-
Rev. 1.3 March 2007
K7R643682M
K7R641882M
K7R640982M
2Mx36 & 4Mx18 & 8Mx9 QDR
TM
II b2 SRAM
2Mx36-bit, 4Mx18-bit, 8Mx9-bit QDR
TM
II b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future fre-
quency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/
-0.1V for 1.8V I/O.
• Separate independent read and write data ports
with concurrent read and write operation
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed early write.
• Registered address, control and data input/output.
• DDR (Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks (K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write function.
• Separate read/write control pin (R and W)
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 15x17mm
& Lead Free
Org.
Part
Number
K7R643682M-F(E)C(I)25
X36 K7R643682M-F(E)C(I)20
K7R643682M-F(E)C(I)16
K7R641882M-F(E)C(I)25
X18 K7R641882M-F(E)C(I)20
K7R641882M-F(E)C(I)16
K7R640982M-F(E)C(I)25
X9 K7R640982M-F(E)C(I)20
K7R640982M-F(E)C(I)16
Cycle Access
RoHS
Unit
Time Time
Avail.
4.0
5.0
6.0
4.0
5.0
6.0
4.0
5.0
6.0
0.45
0.45
0.50
0.45
0.45
0.50
0.45
0.45
0.50
ns
ns
ns
ns
ns
ns
ns
ns
ns
√
√
•
√
√
•
√
√
•
* -F(E)C(I)
F(E) [Package type]: E-Pb Free, F-Pb
C(I) [Operating Temperature]: C-Commercial, I-Industrial
FUNCTIONAL BLOCK DIAGRAM
36 (or 18, 9)
DATA
REG
D (Data in)
36 (or 18,9)
20
(or 21,22)
WRITE/READ DECODE
36 (or 18, 9)
WRITE DRIVER
20 (or 21, 22)
ADDRESS
ADD
REG
OUTPUT SELECT
R
W
BW
X
4(or 2)
CTRL
LOGIC
2Mx36
(4Mx18)
MEMORY
ARRAY
OUTPUT DRIVER
SENSE AMPS
OUTPUT REG
72
(or 36,
18)
72
(or 36,
18)
36 (or 18, 9)
Q (Data Out)
CQ, CQ
K
K
C
C
(Echo Clock out)
CLK
GEN
SELECT OUTPUT CONTROL
Notes:
1. Numbers in ( ) are for x18 device, x9 device also the same with appropriate adjustments of depth and width.
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
-3-
Rev. 1.3 March 2007
K7R643682M
K7R641882M
K7R640982M
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
Doff
D31
Q32
Q33
D33
D34
Q35
TDO
2
NC/SA*
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
SA
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
2Mx36 & 4Mx18 & 8Mx9 QDR
TM
II b2 SRAM
5
BW
2
BW
3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
BW
1
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
NC/SA*
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
PIN CONFIGURATIONS
(TOP VIEW)
K7R643682M(2Mx36)
Notes:
1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 10A for 144Mb and 2A for 288Mb.
2. BW
0
controls write to D0:D8, BW
1
controls write to D9:D17, BW
2
controls write to D18:D26 and BW
3
controls write to D27:D35.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-35
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
1C,1D,2E,1G,1J,2K,1M,1N,2P
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
4A
8A
7B,7A,5A,5B
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,8M,4N,8N
10R
11R
2R
1R
2A,10A
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
1
NOTE
Q0-35
W
R
BW
0
, BW
1,
BW
2
, BW
3
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
NC
Data Outputs
Write Control Pin, active when low
Read Control Pin, active when low
Block Write Control Pin, active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply (1.8 V)
Output Power Supply (1.5V or 1.8V)
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
2
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-4-
Rev. 1.3 March 2007
K7R643682M
K7R641882M
K7R640982M
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA*
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
SA
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
2Mx36 & 4Mx18 & 8Mx9 QDR
TM
II b2 SRAM
5
BW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
PIN CONFIGURATIONS
(TOP VIEW)
K7R641882M(4Mx18)
Notes:
1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 2A for 144Mb.
2. BW
0
controls write to D0:D8 and BW
1
controls write to D9:D17.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-17
Q0-17
W
R
BW
0
, BW
1
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
NC
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
2A,7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,
10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M,2M,
9M,1N,9N,10N,1P,2P,9P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
Data Outputs
Write Control Pin, active when low
Read Control Pin, active when low
Block Write Control Pin, active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply (1.8 V)
Output Power Supply (1.5V or 1.8V)
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
2
1
NOTE
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-5-
Rev. 1.3 March 2007
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