IDT54FCT162511AT datasheet, PDF

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IDT54FCT162511AT: DescriptionFAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY; File Size133KB，11 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT54FCT162511AT Overview

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

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Integrated Device Technology, Inc.

FAST CMOS 16-BIT

REGISTERED/LATCHED

TRANSCEIVER WITH PARITY

IDT54/74FCT162511AT/CT

FEATURES:

•

0.5 MICRON CMOS Technology

Typical tsk(o) (Output Skew) < 250ps, clocked mode

Low input and output leakage

≤1µA

(max)

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,

15.7 mil pitch TVSOP and 25 mil pitch Cerpack

Extended commercial range of –40°C to +85°C

= 5V

±10%

Balanced Output Drivers:

±24mA

(commercial)

±16mA

(military)

Series current limiting resistors

Generate/Check, Check/Check modes

Open drain parity error allows wire-OR

DESCRIPTION:

The FCT162511AT/CT 16-bit registered/latched transceiver

with parity is built using advanced dual metal CMOS technol-

ogy. This high-speed, low-power transceiver combines D-

type latches and D-type flip-flops to allow data flow in transpar-

ent, latched or clocked modes. The device has a parity

generator/cheker in the A-to-B direction and a parity checker

in the B-to-A direction. Error checking is done at the byte level

with separate parity bits for each byte. Separate error flags

exits for each direction with a single error flag indicating an

error for either byte in the A-to-B direction and a second error

flag indicating an error for either byte in the B-to-A direction.

The parity error flags are open drain outputs which can be tied

together and/or tied with flags from other devices to form a

single error flag or interrupt. The parity error flags are enabled

by the

OExx

control pins allowing the designer to disable the

error flag during combinational transitions.

The control pins LEAB, CLKAB and

OEAB

control opera-

tion in the A-to-B direction while LEBA, CLKBA and

OEBA

control the B-to-A direction.

GEN

/CHK is only for the selection

of A-to-B operation, the B-to-A direction is always in checking

mode. The ODD/

EVEN

select is common between the two

directions. Except for the ODD/

EVEN

control, independent

operation can be achieved between the two directions by

using the corresponding control lines.

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM:

LEAB

CLKAB

Data

Parity

GEN/CHK

Byte

Parity

Generator/

Checker

Latch/

Parity, data

OEAB

B0-15

PB1,2

PERB

(Open Drain)

A0-15

PA1,2

ODD/EVEN

LEBA

CLKBA

Parity, data

OEBA

PERA

(Open Drain)

Latch/

Byte

Parity

Checking

Parity, Data

2916 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc.

AUGUST 1996

DSC–2916/5

5.11

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