IDT54FCT162H501ETPF datasheet, PDF

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IDT54FCT162H501ETPF: DescriptionFAST CMOS 18-BIT REGISTERED TRANSCEIVER; File Size91KB，9 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT54FCT162H501ETPF Overview

FAST CMOS 18-BIT REGISTERED TRANSCEIVER

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FAST CMOS

18-BIT REGISTERED

TRANSCEIVER

Integrated Device Technology, Inc.

IDT54/74FCT16501AT/CT/ET

IDT54/74FCT162501AT/CT/ET

IDT54/74FCT162H501AT/CT/ET

CMOS technology. These high-speed, low-power 18-bit reg-

istered bus transceivers combine D-type latches and D-type

• Common features:

flip-flops to allow data flow in transparent, latched and clocked

– 0.5 MICRON CMOS Technology

modes. Data flow in each direction is controlled by output-

– High-speed, low-power CMOS replacement for

enable (OEAB and

OEBA

), latch enable (LEAB and LEBA)

ABT functions

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow,

–

Typical t

(o) (Output Skew) < 250ps

the device operates in transparent mode when LEAB is HIGH.

– Low input and output leakage

≤

1µA (max.)

When LEAB is LOW, the A data is latched if CLKAB is held at

– ESD > 2000V per MIL-STD-883, Method 3015;

a HIGH or LOW logic level. If LEAB is LOW, the A bus data

> 200V using machine model (C = 200pF, R = 0)

is stored in the latch/flip-flop on the LOW-to-HIGH transition of

– Packages include 25 mil pitch SSOP, 19.6 mil pitch

TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack CLKAB. OEAB is the output enable for the B port. Data flow

from the B port to the A port is similar but requires using

OEBA

– Extended commercial range of -40°C to +85°C

LEBA and CLKBA. Flow-through organization of signal pins

• Features for FCT16501AT/CT/ET:

simplifies layout. All inputs are designed with hysteresis for

– High drive outputs (-32mA I

, 64mA I

)

improved noise margin.

– Power off disable outputs permit “live insertion”

The FCT16501AT/CT/ET are ideally suited for driving

– Typical V

OLP

(Output Ground Bounce) < 1.0V at

high-capacitance loads and low-impedance backplanes. The

= 5V, T

= 25°C

output buffers are designed with power off disable capability

• Features for FCT162501AT/CT/ET:

to allow "live insertion" of boards when used as backplane

– Balanced Output Drivers:

±24mA

(commercial),

drivers.

±16mA

(military)

The FCT162501AT/CT/ET have balanced output drive

– Reduced system switching noise

with current limiting resistors. This offers low ground bounce,

– Typical V

OLP

(Output Ground Bounce) < 0.6V at

minimal undershoot, and controlled output fall times–reducing

= 5V,T

= 25°C

the need for external series terminating resistors. The

• Features for FCT162H501AT/CT/ET:

FCT162501AT/CT/ET are plug-in replacements for the

– Bus Hold retains last active bus state during 3-state

FCT16501AT/CT/ET and ABT16501 for on-board bus inter-

– Eliminates the need for external pull up resistors

face applications.

The FCT162H501AT/CT/ET have "Bus Hold" which re-

DESCRIPTION:

tains the input's last state whenever the input goes to high

The FCT16501AT/CT/ET and FCT162501AT/CT/ET 18- impedance. This prevents "floating" inputs and eliminates the

bit registered transceivers are built using advanced dual metal need for pull-up/down resistors.

FEATURES:

FUNCTIONAL BLOCK DIAGRAM

OEAB

CLKBA

LEBA

OEBA

CLKAB

LEAB

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

TO 17 OTHER CHANNELS

2547 drw 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc.

AUGUST 1996

DSC-2547/8

5.10

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