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IDT54FCT16500ATE

Description
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
File Size80KB,8 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet View All

IDT54FCT16500ATE Overview

FAST CMOS 18-BIT REGISTERED TRANSCEIVER

FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
Integrated Device Technology, Inc.
IDT54/74FCT16500AT/CT/ET
IDT54/74FCT162500AT/CT/ET
bit registered transceivers are built using advanced dual metal
CMOS technology. These high-speed, low-power 18-bit reg-
• Common features:
istered bus transceivers combine D-type latches and D-type
– 0.5 MICRON CMOS Technology
flip-flops to allow data flow in transparent, latched and clocked
– High-speed, low-power CMOS replacement for
modes. Data flow in each direction is controlled by output-
ABT functions
enable (OEAB and
OEBA
), latch enable (LEAB and LEBA)
Typical t
SK
(o) (Output Skew) < 250ps
and clock (
CLKAB
and
CLKBA
) inputs. For A-to-B data flow,
– Low input and output leakage
≤1µA
(max.)
the device operates in transparent mode when LEAB is HIGH.
– ESD > 2000V per MIL-STD-883, Method 3015;
When LEAB is LOW, the A data is latched if
CLKAB
is held at
> 200V using machine model (C = 200pF, R = 0)
a HIGH or LOW logic level. If LEAB is LOW, the A bus data is
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack stored in the latch/flip-flop on the HIGH-to-LOW transition of
CLKAB
. OEAB performs the output enable function on the B
– Extended commercial range of -40°C to +85°C
port. Data flow from B port to A port is similar but uses
OEBA
,
– V
CC
= 5V
±10%
LEBA and
CLKBA
. Flow-through organization of signal pins
• Features for FCT16500AT/CT/ET:
simplifies layout. All inputs are designed with hysteresis for
– High drive outputs (-32mA I
OH
, 64mA I
OL
)
improved noise margin.
– Power off disable outputs permit “live insertion”
The FCT16500AT/CT/ET are ideally suited for driving
– Typical V
OLP
(Output Ground Bounce) < 1.0V at
high-capacitance loads and low-impedance backplanes. The
V
CC
= 5V, T
A
= 25°C
output buffers are designed with power off disable capability
• Features for FCT162500AT/CT/ET:
to allow "live insertion" of boards when used as backplane
– Balanced Output Drivers:
±24mA
(commercial),
drivers.
±16mA
(military)
The FCT162500AT/CT/ET have balanced output drive
– Reduced system switching noise
with current limiting resistors. This offers low ground bounce,
– Typical V
OLP
(Output Ground Bounce) < 0.6V at
minimal undershoot, and controlled output fall times–reducing
V
CC
= 5V,T
A
= 25°C
the need for external series terminating resistors. The
FCT162500AT/CT/ET are plug-in replacements for the
DESCRIPTION:
FCT16500AT/CT/ET and ABT16500 for on-board bus inter-
The FCT16500AT/CT/ET and FCT162500AT/CT/ET 18- face applications.
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
A
1
D
C
B
1
D
C
D
C
D
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
2548 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-2548/7
5.9
1
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